BibTeX records: Shunitsu Kohara

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@inproceedings{DBLP:conf/islped/TakaseZGKATKKKITT11,
  author       = {Hideki Takase and
                  Gang Zeng and
                  Lovic Gauthier and
                  Hirotaka Kawashima and
                  Noritoshi Atsumi and
                  Tomohiro Tatematsu and
                  Yoshitake Kobayashi and
                  Shunitsu Kohara and
                  Takenori Koshiro and
                  Tohru Ishihara and
                  Hiroyuki Tomiyama and
                  Hiroaki Takada},
  editor       = {Naehyuck Chang and
                  Hiroshi Nakamura and
                  Koji Inoue and
                  Kenichi Osada and
                  Massimo Poncino},
  title        = {An integrated optimization framework for reducing the energy consumption
                  of embedded real-time applications},
  booktitle    = {Proceedings of the 2011 International Symposium on Low Power Electronics
                  and Design, 2011, Fukuoka, Japan, August 1-3, 2011},
  pages        = {271--276},
  publisher    = {{IEEE/ACM}},
  year         = {2011},
  url          = {http://portal.acm.org/citation.cfm?id=2016863\&\#38;CFID=34981777\&\#38;CFTOKEN=25607807},
  timestamp    = {Mon, 13 Aug 2012 09:40:34 +0200},
  biburl       = {https://dblp.org/rec/conf/islped/TakaseZGKATKKKITT11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ieicet/TanimuraNKSTYO09,
  author       = {Kazuyuki Tanimura and
                  Ryuta Nara and
                  Shunitsu Kohara and
                  Youhua Shi and
                  Nozomu Togawa and
                  Masao Yanagisawa and
                  Tatsuo Ohtsuki},
  title        = {Unified Dual-Radix Architecture for Scalable Montgomery Multiplications
                  in \emph{GF}(\emph{P}) and \emph{GF}(2\({}^{\mbox{\emph{n}}}\))},
  journal      = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
  volume       = {92-A},
  number       = {9},
  pages        = {2304--2317},
  year         = {2009},
  url          = {https://doi.org/10.1587/transfun.E92.A.2304},
  doi          = {10.1587/TRANSFUN.E92.A.2304},
  timestamp    = {Mon, 28 Aug 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ieicet/TanimuraNKSTYO09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/imt/OhchiKTYO08,
  author       = {Akira Ohchi and
                  Shunitsu Kohara and
                  Nozomu Togawa and
                  Masao Yanagisawa and
                  Tatsuo Ohtsuki},
  title        = {Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register
                  Architectures},
  journal      = {Inf. Media Technol.},
  volume       = {3},
  number       = {4},
  pages        = {691--703},
  year         = {2008},
  url          = {https://doi.org/10.11185/imt.3.691},
  doi          = {10.11185/IMT.3.691},
  timestamp    = {Wed, 28 Aug 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/imt/OhchiKTYO08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ipsj/OhchiKTYO08,
  author       = {Akira Ohchi and
                  Shunitsu Kohara and
                  Nozomu Togawa and
                  Masao Yanagisawa and
                  Tatsuo Ohtsuki},
  title        = {Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register
                  Architectures},
  journal      = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
  volume       = {1},
  pages        = {78--90},
  year         = {2008},
  url          = {https://doi.org/10.2197/ipsjtsldm.1.78},
  doi          = {10.2197/IPSJTSLDM.1.78},
  timestamp    = {Mon, 26 Oct 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/ipsj/OhchiKTYO08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/aspdac/TanimuraNKSSTYO08,
  author       = {Kazuyuki Tanimura and
                  Ryuta Nara and
                  Shunitsu Kohara and
                  Kazunori Shimizu and
                  Youhua Shi and
                  Nozomu Togawa and
                  Masao Yanagisawa and
                  Tatsuo Ohtsuki},
  editor       = {Chong{-}Min Kyung and
                  Kiyoung Choi and
                  Soonhoi Ha},
  title        = {Scalable unified dual-radix architecture for Montgomery multiplication
                  in {GF(P)} and GF(2\({}^{\mbox{n}}\))},
  booktitle    = {Proceedings of the 13th Asia South Pacific Design Automation Conference,
                  {ASP-DAC} 2008, Seoul, Korea, January 21-24, 2008},
  pages        = {697--702},
  publisher    = {{IEEE}},
  year         = {2008},
  url          = {https://doi.org/10.1109/ASPDAC.2008.4484041},
  doi          = {10.1109/ASPDAC.2008.4484041},
  timestamp    = {Sun, 25 Oct 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/aspdac/TanimuraNKSSTYO08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/aspdac/KoharaTUMTYO06,
  author       = {Shunitsu Kohara and
                  Naoki Tomono and
                  Jumpei Uchida and
                  Yuichiro Miyaoka and
                  Nozomu Togawa and
                  Masao Yanagisawa and
                  Tatsuo Ohtsuki},
  editor       = {Fumiyasu Hirose},
  title        = {An interface-circuit synthesis method with configurable processor
                  core in IP-based SoC designs},
  booktitle    = {Proceedings of the 2006 Conference on Asia South Pacific Design Automation:
                  {ASP-DAC} 2006, Yokohama, Japan, January 24-27, 2006},
  pages        = {594--599},
  publisher    = {{IEEE}},
  year         = {2006},
  url          = {https://doi.org/10.1109/ASPDAC.2006.1594750},
  doi          = {10.1109/ASPDAC.2006.1594750},
  timestamp    = {Wed, 16 Oct 2019 14:14:52 +0200},
  biburl       = {https://dblp.org/rec/conf/aspdac/KoharaTUMTYO06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/aspdac/TomonoKUMTYO05,
  author       = {Naoki Tomono and
                  Shunitsu Kohara and
                  Jumpei Uchida and
                  Yuichiro Miyaoka and
                  Nozomu Togawa and
                  Masao Yanagisawa and
                  Tatsuo Ohtsuki},
  editor       = {Tingao Tang},
  title        = {A processor core synthesis system in IP-based SoC design},
  booktitle    = {Proceedings of the 2005 Conference on Asia South Pacific Design Automation,
                  {ASP-DAC} 2005, Shanghai, China, January 18-21, 2005},
  pages        = {286--291},
  publisher    = {{ACM} Press},
  year         = {2005},
  url          = {https://doi.org/10.1145/1120725.1120851},
  doi          = {10.1145/1120725.1120851},
  timestamp    = {Wed, 16 Oct 2019 14:14:52 +0200},
  biburl       = {https://dblp.org/rec/conf/aspdac/TomonoKUMTYO05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}