BibTeX records: Kyehyun Kyung

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@inproceedings{DBLP:conf/isscc/KangKJJPCSKKKLK19,
  author    = {Dongku Kang and
               Minsu Kim and
               Suchang Jeon and
               Wontaeck Jung and
               Jooyong Park and
               Gyo Soo Choo and
               Dong{-}Kyo Shim and
               Anil Kavala and
               Seungbum Kim and
               Kyung{-}Min Kang and
               Jiyoung Lee and
               Kuihan Ko and
               Hyun Wook Park and
               ByungJun Min and
               Changyeon Yu and
               Sewon Yun and
               Nahyun Kim and
               Yeonwook Jung and
               Sungwhan Seo and
               Sunghoon Kim and
               Moo Kyung Lee and
               Joo{-}Yong Park and
               James C. Kim and
               Young San Cha and
               Kwangwon Kim and
               Youngmin Jo and
               Hyun{-}Jin Kim and
               Youngdon Choi and
               Jindo Byun and
               Ji{-}hyun Park and
               Kiwon Kim and
               Tae{-}Hong Kwon and
               Young{-}Sun Min and
               Chiweon Yoon and
               Youngcho Kim and
               Dong{-}Hun Kwak and
               Eungsuk Lee and
               Wook{-}Ghee Hahn and
               Ki{-}Sung Kim and
               Kyungmin Kim and
               Euisang Yoon and
               Wontae Kim and
               Inryul Lee and
               Seunghyun Moon and
               Jeong{-}Don Ihm and
               Dae{-}Seok Byeon and
               Ki{-}Whan Song and
               Sangjoon Hwang and
               Kyehyun Kyung},
  title     = {A 512Gb 3-bit/Cell 3D 6\({}^{\mbox{th}}\)-Generation {V-NAND} Flash
               Memory with 82MB/s Write Throughput and 1.2Gb/s Interface},
  booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2019,
               San Francisco, CA, USA, February 17-21, 2019},
  pages     = {216--218},
  year      = {2019},
  crossref  = {DBLP:conf/isscc/2019},
  url       = {https://doi.org/10.1109/ISSCC.2019.8662493},
  doi       = {10.1109/ISSCC.2019.8662493},
  timestamp = {Tue, 12 Mar 2019 14:13:49 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/isscc/KangKJJPCSKKKLK19},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KimKJKPPLPALKYY18,
  author    = {Chulbum Kim and
               Doo{-}Hyun Kim and
               Woopyo Jeong and
               Hyun{-}Jin Kim and
               Il{-}Han Park and
               Hyun Wook Park and
               Jong{-}Hoon Lee and
               Jiyoon Park and
               Yang{-}Lo Ahn and
               Ji Young Lee and
               Seungbum Kim and
               Hyun{-}Jun Yoon and
               Jaedoeg Yu and
               Nayoung Choi and
               Nahyun Kim and
               Hwajun Jang and
               Jonghoon Park and
               Seunghwan Song and
               Yongha Park and
               Jinbae Bang and
               Sanggi Hong and
               Youngdon Choi and
               Moosung Kim and
               Hyunggon Kim and
               Pansuk Kwak and
               Jeong{-}Don Ihm and
               Dae{-}Seok Byeon and
               Jin{-}yub Lee and
               Ki{-}Tae Park and
               Kyehyun Kyung},
  title     = {A 512-Gb 3-b/Cell 64-Stacked {WL} 3-D-NAND Flash Memory},
  journal   = {J. Solid-State Circuits},
  volume    = {53},
  number    = {1},
  pages     = {124--133},
  year      = {2018},
  url       = {https://doi.org/10.1109/JSSC.2017.2731813},
  doi       = {10.1109/JSSC.2017.2731813},
  timestamp = {Thu, 25 Jan 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/journals/jssc/KimKJKPPLPALKYY18},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/LeeKKJJKLKPLKLL18,
  author    = {Seungjae Lee and
               Chulbum Kim and
               Minsu Kim and
               Sung{-}Min Joe and
               Joonsuc Jang and
               Seungbum Kim and
               Kangbin Lee and
               Jisu Kim and
               Jiyoon Park and
               Hanjun Lee and
               Min{-}Seok Kim and
               Seonyong Lee and
               SeonGeon Lee and
               Jinbae Bang and
               Dongjin Shin and
               Hwajun Jang and
               Deokwoo Lee and
               Nahyun Kim and
               Jonghoo Jo and
               Jonghoon Park and
               Sohyun Park and
               Youngsik Rho and
               Yongha Park and
               Ho{-}joon Kim and
               Cheon An Lee and
               Chungho Yu and
               Young{-}Sun Min and
               Moosung Kim and
               Kyungmin Kim and
               Seunghyun Moon and
               Hyun{-}Jin Kim and
               Youngdon Choi and
               YoungHwan Ryu and
               Jinwon Choi and
               Minyeong Lee and
               Jungkwan Kim and
               Gyo Soo Choo and
               Jeong{-}Don Lim and
               Dae{-}Seok Byeon and
               Ki{-}Whan Song and
               Ki{-}Tae Park and
               Kyehyun Kyung},
  title     = {A 1Tb 4b/cell 64-stacked-WL 3D {NAND} flash memory with 12MB/s program
               throughput},
  booktitle = {2018 {IEEE} International Solid-State Circuits Conference, {ISSCC}
               2018, San Francisco, CA, USA, February 11-15, 2018},
  pages     = {340--342},
  year      = {2018},
  crossref  = {DBLP:conf/isscc/2018},
  url       = {https://doi.org/10.1109/ISSCC.2018.8310323},
  doi       = {10.1109/ISSCC.2018.8310323},
  timestamp = {Thu, 15 Mar 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/isscc/LeeKKJJKLKPLKLL18},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KangJKKCKRKLKLY17,
  author    = {Dongku Kang and
               Woopyo Jeong and
               Chulbum Kim and
               Doo{-}Hyun Kim and
               Yong{-}Sung Cho and
               Kyung{-}Tae Kang and
               Jinho Ryu and
               Kyung{-}Min Kang and
               Sungyeon Lee and
               Wandong Kim and
               Hanjun Lee and
               Jaedoeg Yu and
               Nayoung Choi and
               Dong{-}Su Jang and
               Cheon An Lee and
               Young{-}Sun Min and
               Moosung Kim and
               Ansoo Park and
               Jae{-}Ick Son and
               In{-}Mo Kim and
               Pansuk Kwak and
               Bong{-}Kil Jung and
               Doosub Lee and
               Hyunggon Kim and
               Jeong{-}Don Ihm and
               Dae{-}Seok Byeon and
               Jin{-}Yup Lee and
               Ki{-}Tae Park and
               Kyehyun Kyung},
  title     = {256 Gb 3 b/Cell V-nand Flash Memory With 48 Stacked {WL} Layers},
  journal   = {J. Solid-State Circuits},
  volume    = {52},
  number    = {1},
  pages     = {210--217},
  year      = {2017},
  url       = {https://doi.org/10.1109/JSSC.2016.2604297},
  doi       = {10.1109/JSSC.2016.2604297},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/jssc/KangJKKCKRKLKLY17},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KimCJPPKKLLKPAL17,
  author    = {Chulbum Kim and
               Ji{-}Ho Cho and
               Woopyo Jeong and
               Il{-}Han Park and
               Hyun Wook Park and
               Doo{-}Hyun Kim and
               Daewoon Kang and
               Sunghoon Lee and
               Ji{-}Sang Lee and
               Wontae Kim and
               Jiyoon Park and
               Yang{-}Lo Ahn and
               Jiyoung Lee and
               Jong{-}Hoon Lee and
               Seungbum Kim and
               Hyun{-}Jun Yoon and
               Jaedoeg Yu and
               Nayoung Choi and
               Yelim Kwon and
               Nahyun Kim and
               Hwajun Jang and
               Jonghoon Park and
               Seunghwan Song and
               Yongha Park and
               Jinbae Bang and
               Sangki Hong and
               Byunghoon Jeong and
               Hyun{-}Jin Kim and
               Chunan Lee and
               Young{-}Sun Min and
               Inryul Lee and
               In{-}Mo Kim and
               Sung{-}Hoon Kim and
               Dongkyu Yoon and
               Ki{-}Sung Kim and
               Youngdon Choi and
               Moosung Kim and
               Hyunggon Kim and
               Pansuk Kwak and
               Jeong{-}Don Ihm and
               Dae{-}Seok Byeon and
               Jin{-}yub Lee and
               Ki{-}Tae Park and
               Kyehyun Kyung},
  title     = {11.4 {A} 512Gb 3b/cell 64-stacked {WL} 3D {V-NAND} flash memory},
  booktitle = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC}
               2017, San Francisco, CA, USA, February 5-9, 2017},
  pages     = {202--203},
  year      = {2017},
  crossref  = {DBLP:conf/isscc/2017},
  url       = {https://doi.org/10.1109/ISSCC.2017.7870331},
  doi       = {10.1109/ISSCC.2017.7870331},
  timestamp = {Wed, 17 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isscc/KimCJPPKKLLKPAL17},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/JeongIKNSCYKKPK16,
  author    = {Woopyo Jeong and
               Jae{-}Woo Im and
               Doo{-}Hyun Kim and
               Sangwan Nam and
               Dong{-}Kyo Shim and
               Myung{-}Hoon Choi and
               Hyun{-}Jun Yoon and
               Dae{-}Han Kim and
               Youse Kim and
               Hyun Wook Park and
               Dong{-}Hun Kwak and
               Sang{-}Won Park and
               Seok{-}Min Yoon and
               Wook{-}Ghee Hahn and
               Jinho Ryu and
               Sang{-}Won Shim and
               Kyung{-}Tae Kang and
               Jeong{-}Don Ihm and
               In{-}Mo Kim and
               Doosub Lee and
               Ji{-}Ho Cho and
               Moosung Kim and
               Jae{-}hoon Jang and
               Sang{-}Won Hwang and
               Dae{-}Seok Byeon and
               Hyang{-}Ja Yang and
               Ki{-}Tae Park and
               Kyehyun Kyung and
               Jeong{-}Hyuk Choi},
  title     = {A 128 Gb 3b/cell {V-NAND} Flash Memory With 1 Gb/s {I/O} Rate},
  journal   = {J. Solid-State Circuits},
  volume    = {51},
  number    = {1},
  pages     = {204--212},
  year      = {2016},
  url       = {https://doi.org/10.1109/JSSC.2015.2474117},
  doi       = {10.1109/JSSC.2015.2474117},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/jssc/JeongIKNSCYKKPK16},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KangJKKCKRKLKLY16,
  author    = {Dongku Kang and
               Woopyo Jeong and
               Chulbum Kim and
               Doo{-}Hyun Kim and
               Yong{-}Sung Cho and
               Kyung{-}Tae Kang and
               Jinho Ryu and
               Kyung{-}Min Kang and
               Sungyeon Lee and
               Wandong Kim and
               Hanjun Lee and
               Jaedoeg Yu and
               Nayoung Choi and
               Dong{-}Su Jang and
               Jeong{-}Don Ihm and
               Doo{-}Gon Kim and
               Young{-}Sun Min and
               Moosung Kim and
               Ansoo Park and
               Jae{-}Ick Son and
               In{-}Mo Kim and
               Pansuk Kwak and
               Bong{-}Kil Jung and
               Doosub Lee and
               Hyunggon Kim and
               Hyang{-}Ja Yang and
               Dae{-}Seok Byeon and
               Ki{-}Tae Park and
               Kyehyun Kyung and
               Jeong{-}Hyuk Choi},
  title     = {7.1 256Gb 3b/cell {V-NAND} flash memory with 48 stacked {WL} layers},
  booktitle = {2016 {IEEE} International Solid-State Circuits Conference, {ISSCC}
               2016, San Francisco, CA, USA, January 31 - February 4, 2016},
  pages     = {130--131},
  year      = {2016},
  crossref  = {DBLP:conf/isscc/2016},
  url       = {https://doi.org/10.1109/ISSCC.2016.7417941},
  doi       = {10.1109/ISSCC.2016.7417941},
  timestamp = {Wed, 17 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isscc/KangJKKCKRKLKLY16},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/LeeLPPYKLKLKCCY16,
  author    = {Seungjae Lee and
               Jin{-}yub Lee and
               Il{-}Han Park and
               Jong{-}Yeol Park and
               Sung{-}Won Yun and
               Minsu Kim and
               Jong{-}Hoon Lee and
               Min{-}Seok Kim and
               Kangbin Lee and
               Taeeun Kim and
               Byungkyu Cho and
               Dooho Cho and
               Sangbum Yun and
               Jung{-}No Im and
               Hyejin Yim and
               Kyung{-}hwa Kang and
               Suchang Jeon and
               Sungkyu Jo and
               Yang{-}Lo Ahn and
               Sung{-}Min Joe and
               Suyong Kim and
               Deok{-}kyun Woo and
               Jiyoon Park and
               Hyun Wook Park and
               Youngmin Kim and
               Jonghoon Park and
               Yongsu Choi and
               Makoto Hirano and
               Jeong{-}Don Ihm and
               Byunghoon Jeong and
               Seon{-}Kyoo Lee and
               Moosung Kim and
               Hokil Lee and
               Sungwhan Seo and
               Hongsoo Jeon and
               Chan{-}ho Kim and
               Hyunggon Kim and
               Jintae Kim and
               Yongsik Yim and
               Hoosung Kim and
               Dae{-}Seok Byeon and
               Hyang{-}Ja Yang and
               Ki{-}Tae Park and
               Kyehyun Kyung and
               Jeong{-}Hyuk Choi},
  title     = {7.5 {A} 128Gb 2b/cell {NAND} flash memory in 14nm technology with
               tPROG=640{\(\mathrm{\mu}\)}s and 800MB/s {I/O} rate},
  booktitle = {2016 {IEEE} International Solid-State Circuits Conference, {ISSCC}
               2016, San Francisco, CA, USA, January 31 - February 4, 2016},
  pages     = {138--139},
  year      = {2016},
  crossref  = {DBLP:conf/isscc/2016},
  url       = {https://doi.org/10.1109/ISSCC.2016.7417945},
  doi       = {10.1109/ISSCC.2016.7417945},
  timestamp = {Wed, 17 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isscc/LeeLPPYKLKLKCCY16},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ParkNKKLCCKKKPSKPLYKSARKYKSBCHKCK15,
  author    = {Ki{-}Tae Park and
               Sangwan Nam and
               Dae{-}Han Kim and
               Pansuk Kwak and
               Doosub Lee and
               Yoon{-}Hee Choi and
               Myung{-}Hoon Choi and
               Dong{-}Hun Kwak and
               Doo{-}Hyun Kim and
               Minsu Kim and
               Hyun Wook Park and
               Sang{-}Won Shim and
               Kyung{-}Min Kang and
               Sang{-}Won Park and
               Kangbin Lee and
               Hyun{-}Jun Yoon and
               Kuihan Ko and
               Dong{-}Kyo Shim and
               Yang{-}Lo Ahn and
               Jinho Ryu and
               Donghyun Kim and
               Kyunghwa Yun and
               Joonsoo Kwon and
               Seunghoon Shin and
               Dae{-}Seok Byeon and
               Kihwan Choi and
               Jin{-}Man Han and
               Kyehyun Kyung and
               Jeong{-}Hyuk Choi and
               Kinam Kim},
  title     = {Three-Dimensional 128 Gb {MLC} Vertical nand Flash Memory With 24-WL
               Stacked Layers and 50 MB/s High-Speed Programming},
  journal   = {J. Solid-State Circuits},
  volume    = {50},
  number    = {1},
  pages     = {204--213},
  year      = {2015},
  url       = {https://doi.org/10.1109/JSSC.2014.2352293},
  doi       = {10.1109/JSSC.2014.2352293},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/jssc/ParkNKKLCCKKKPSKPLYKSARKYKSBCHKCK15},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ImJKNSCYKKPKPYH15,
  author    = {Jae{-}Woo Im and
               Woopyo Jeong and
               Doo{-}Hyun Kim and
               Sangwan Nam and
               Dong{-}Kyo Shim and
               Myung{-}Hoon Choi and
               Hyun{-}Jun Yoon and
               Dae{-}Han Kim and
               Youse Kim and
               Hyun Wook Park and
               Dong{-}Hun Kwak and
               Sang{-}Won Park and
               Seok{-}Min Yoon and
               Wook{-}Ghee Hahn and
               Jinho Ryu and
               Sang{-}Won Shim and
               Kyung{-}Tae Kang and
               Sung{-}Ho Choi and
               Jeong{-}Don Ihm and
               Young{-}Sun Min and
               In{-}Mo Kim and
               Doosub Lee and
               Ji{-}Ho Cho and
               Ohsuk Kwon and
               Ji{-}Sang Lee and
               Moosung Kim and
               Sang{-}Hyun Joo and
               Jae{-}hoon Jang and
               Sang{-}Won Hwang and
               Dae{-}Seok Byeon and
               Hyang{-}Ja Yang and
               Ki{-}Tae Park and
               Kyehyun Kyung and
               Jeong{-}Hyuk Choi},
  title     = {7.2 {A} 128Gb 3b/cell {V-NAND} flash memory with 1Gb/s {I/O} rate},
  booktitle = {2015 {IEEE} International Solid-State Circuits Conference, {ISSCC}
               2015, Digest of Technical Papers, San Francisco, CA, USA, February
               22-26, 2015},
  pages     = {1--3},
  year      = {2015},
  crossref  = {DBLP:conf/isscc/2015},
  url       = {https://doi.org/10.1109/ISSCC.2015.7062960},
  doi       = {10.1109/ISSCC.2015.7062960},
  timestamp = {Wed, 17 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isscc/ImJKNSCYKKPKPYH15},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KimLLNSKYSLRKKP15,
  author    = {Hyun{-}Jin Kim and
               Jeong{-}Don Lim and
               Jang{-}Woo Lee and
               Dae{-}Hoon Na and
               Joon{-}Ho Shin and
               Chae{-}Hoon Kim and
               Seungwoo Yu and
               Ji{-}Yeon Shin and
               Seon{-}Kyoo Lee and
               Devraj Rajagopal and
               Sang{-}Tae Kim and
               Kyeong{-}Tae Kang and
               Jeong{-}Joon Park and
               Yongjin Kwon and
               Min{-}Jae Lee and
               Sunghoon Kim and
               Seunghoon Shin and
               Hyunggon Kim and
               Jin{-}Tae Kim and
               Ki{-}Sung Kim and
               Han{-}Sung Joo and
               Chan{-}Jin Park and
               Jae{-}Hwan Kim and
               Man{-}Joong Lee and
               Do{-}Kook Kim and
               Hyang{-}Ja Yang and
               Dae{-}Seok Byeon and
               Ki{-}Tae Park and
               Kyehyun Kyung and
               Jeong{-}Hyuk Choi},
  title     = {7.6 1GB/s 2Tb {NAND} flash multi-chip package with frequency-boosting
               interface chip},
  booktitle = {2015 {IEEE} International Solid-State Circuits Conference, {ISSCC}
               2015, Digest of Technical Papers, San Francisco, CA, USA, February
               22-26, 2015},
  pages     = {1--3},
  year      = {2015},
  crossref  = {DBLP:conf/isscc/2015},
  url       = {https://doi.org/10.1109/ISSCC.2015.7062964},
  doi       = {10.1109/ISSCC.2015.7062964},
  timestamp = {Wed, 17 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isscc/KimLLNSKYSLRKKP15},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChoPYLJSCHKJ13,
  author    = {Yong{-}Sung Cho and
               Il{-}Han Park and
               Sangyong Yoon and
               Nam{-}Hee Lee and
               Sang{-}Hyun Joo and
               Ki{-}Whan Song and
               Kihwan Choi and
               Jin{-}Man Han and
               Kyehyun Kyung and
               Young{-}Hyun Jun},
  title     = {Adaptive Multi-Pulse Program Scheme Based on Tunneling Speed Classification
               for Next Generation Multi-Bit/Cell {NAND} {FLASH}},
  journal   = {J. Solid-State Circuits},
  volume    = {48},
  number    = {4},
  pages     = {948--959},
  year      = {2013},
  url       = {https://doi.org/10.1109/JSSC.2013.2237974},
  doi       = {10.1109/JSSC.2013.2237974},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/jssc/ChoPYLJSCHKJ13},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KimRLKLJSJKLLKCYCJPHSKLJ12,
  author    = {Chulbum Kim and
               Jinho Ryu and
               Tae{-}Sung Lee and
               Hyunggon Kim and
               Jaewoo Lim and
               Jaeyong Jeong and
               Seonghwan Seo and
               Hongsoo Jeon and
               Bokeun Kim and
               Inyoul Lee and
               Dooseop Lee and
               Pansuk Kwak and
               Seongsoon Cho and
               Yongsik Yim and
               Changhyun Cho and
               Woopyo Jeong and
               Kwang{-}Il Park and
               Jin{-}Man Han and
               Duheon Song and
               Kyehyun Kyung and
               Youngho Lim and
               Young{-}Hyun Jun},
  title     = {A 21 nm High Performance 64 Gb {MLC} {NAND} Flash Memory With 400
               MB/s Asynchronous Toggle {DDR} Interface},
  journal   = {J. Solid-State Circuits},
  volume    = {47},
  number    = {4},
  pages     = {981--989},
  year      = {2012},
  url       = {https://doi.org/10.1109/JSSC.2012.2185341},
  doi       = {10.1109/JSSC.2012.2185341},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/jssc/KimRLKLJSJKLLKCYCJPHSKLJ12},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/LeeCYJJHPKYLMYLPKYKCKJCIKHPYLLKKSJCHKLJ12,
  author    = {Daeyeal Lee and
               Ik Joon Chang and
               Sangyong Yoon and
               Joonsuc Jang and
               Dong{-}Su Jang and
               Wook{-}Ghee Hahn and
               Jong{-}Yeol Park and
               Doo{-}Gon Kim and
               Chiweon Yoon and
               Bong{-}Soon Lim and
               ByungJun Min and
               Sung{-}Won Yun and
               Ji{-}Sang Lee and
               Il{-}Han Park and
               Kyung{-}Ryun Kim and
               Jeong{-}Yun Yun and
               Youse Kim and
               Yong{-}Sung Cho and
               Kyung{-}Min Kang and
               Sang{-}Hyun Joo and
               Jin{-}Young Chun and
               Jung{-}No Im and
               Seunghyuk Kwon and
               Seokjun Ham and
               Ansoo Park and
               Jae{-}Duk Yu and
               Nam{-}Hee Lee and
               Tae{-}Sung Lee and
               Moosung Kim and
               Hoosung Kim and
               Ki{-}Whan Song and
               Byung{-}Gil Jeon and
               Kihwan Choi and
               Jin{-}Man Han and
               Kyehyun Kyung and
               Youngho Lim and
               Young{-}Hyun Jun},
  title     = {A 64Gb 533Mb/s {DDR} interface {MLC} {NAND} Flash in sub-20nm technology},
  booktitle = {2012 {IEEE} International Solid-State Circuits Conference, {ISSCC}
               2012, San Francisco, CA, USA, February 19-23, 2012},
  pages     = {430--432},
  year      = {2012},
  crossref  = {DBLP:conf/isscc/2012},
  url       = {https://doi.org/10.1109/ISSCC.2012.6177077},
  doi       = {10.1109/ISSCC.2012.6177077},
  timestamp = {Wed, 17 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isscc/LeeCYJJHPKYLMYLPKYKCKJCIKHPYLLKKSJCHKLJ12},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ShinSJKYCKPYSCS12,
  author    = {Seung{-}Hwan Shin and
               Dong{-}Kyo Shim and
               Jaeyong Jeong and
               Ohsuk Kwon and
               Sangyong Yoon and
               Myung{-}Hoon Choi and
               Tae{-}Young Kim and
               Hyun Wook Park and
               Hyun{-}Jun Yoon and
               Youngsun Song and
               Yoon{-}Hee Choi and
               Sang{-}Won Shim and
               Yang{-}Lo Ahn and
               Ki{-}Tae Park and
               Jin{-}Man Han and
               Kyehyun Kyung and
               Young{-}Hyun Jun},
  title     = {A new 3-bit programming algorithm using SLC-to-TLC migration for 8MB/s
               high performance {TLC} {NAND} flash memory},
  booktitle = {Symposium on {VLSI} Circuits, {VLSIC} 2012, Honolulu, HI, USA, June
               13-15, 2012},
  pages     = {132--133},
  year      = {2012},
  crossref  = {DBLP:conf/vlsic/2012},
  url       = {https://doi.org/10.1109/VLSIC.2012.6243825},
  doi       = {10.1109/VLSIC.2012.6243825},
  timestamp = {Sun, 21 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/vlsic/ShinSJKYCKPYSCS12},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ChoPYLJSCHKJ12,
  author    = {Yong{-}Sung Cho and
               Il{-}Han Park and
               Sangyong Yoon and
               Nam{-}Hee Lee and
               Sang{-}Hyun Joo and
               Ki{-}Whan Song and
               Kihwan Choi and
               Jin{-}Man Han and
               Kyehyun Kyung and
               Young{-}Hyun Jun},
  title     = {Adaptive multi-pulse program scheme based on tunneling speed classification
               for next generation multi-bit/cell {NAND} {FLASH}},
  booktitle = {Symposium on {VLSI} Circuits, {VLSIC} 2012, Honolulu, HI, USA, June
               13-15, 2012},
  pages     = {136--137},
  year      = {2012},
  crossref  = {DBLP:conf/vlsic/2012},
  url       = {https://doi.org/10.1109/VLSIC.2012.6243827},
  doi       = {10.1109/VLSIC.2012.6243827},
  timestamp = {Thu, 26 Oct 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/vlsic/ChoPYLJSCHKJ12},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KimOLLHHNMKPRPKKKBCJHLKCJ11,
  author    = {Jung{-}Sik Kim and
               Chi Sung Oh and
               Hocheol Lee and
               Donghyuk Lee and
               Hyong{-}Ryol Hwang and
               Sooman Hwang and
               Byongwook Na and
               Joungwook Moon and
               Jin{-}Guk Kim and
               Hanna Park and
               Jang{-}Woo Ryu and
               Kiwon Park and
               Sang{-}Kyu Kang and
               So{-}Young Kim and
               Hoyoung Kim and
               Jong{-}Min Bang and
               Hyunyoon Cho and
               Minsoo Jang and
               Cheolmin Han and
               Jung{-}Bae Lee and
               Kyehyun Kyung and
               Joo{-}Sun Choi and
               Young{-}Hyun Jun},
  title     = {A 1.2V 12.8GB/s 2Gb mobile Wide-I/O {DRAM} with 4{\texttimes}128 I/Os
               using TSV-based stacking},
  booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2011,
               Digest of Technical Papers, San Francisco, CA, USA, 20-24 February,
               2011},
  pages     = {496--498},
  year      = {2011},
  crossref  = {DBLP:conf/isscc/2011},
  url       = {https://doi.org/10.1109/ISSCC.2011.5746413},
  doi       = {10.1109/ISSCC.2011.5746413},
  timestamp = {Wed, 17 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isscc/KimOLLHHNMKPRPKKKBCJHLKCJ11},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KimPPKKKLPKCLSLYKYKLKLC10,
  author    = {Hyunggon Kim and
               Jung{-}hoon Park and
               Ki{-}Tae Park and
               Pansuk Kwak and
               Ohsuk Kwon and
               Chulbum Kim and
               Younyeol Lee and
               Sangsoo Park and
               Kyungmin Kim and
               Doohyun Cho and
               Juseok Lee and
               Jungho Song and
               Soowoong Lee and
               Hyukjun Yoo and
               Sanglok Kim and
               Seungwoo Yu and
               Sungjun Kim and
               Sungsoo Lee and
               Kyehyun Kyung and
               Yong{-}Ho Lim and
               Chilhee Chung},
  title     = {A 159mm\({}^{\mbox{2}}\) 32nm 32Gb {MLC} NAND-flash memory with 200MB/s
               asynchronous {DDR} interface},
  booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2010,
               Digest of Technical Papers, San Francisco, CA, USA, 7-11 February,
               2010},
  pages     = {442--443},
  year      = {2010},
  crossref  = {DBLP:conf/isscc/2010},
  url       = {https://doi.org/10.1109/ISSCC.2010.5433912},
  doi       = {10.1109/ISSCC.2010.5433912},
  timestamp = {Wed, 17 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isscc/KimPPKKKLPKCLSLYKYKLKLC10},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/MoonCLJHKJSSCSCKJK09,
  author    = {Yongsam Moon and
               Yong{-}Ho Cho and
               Hyun{-}Bae Lee and
               Byung{-}Hoon Jeong and
               Seok{-}Hun Hyun and
               Byungchul Kim and
               In{-}Chul Jeong and
               Seong{-}Young Seo and
               Junho Shin and
               Seok{-}Woo Choi and
               Ho{-}Sung Song and
               Jung{-}Hwan Choi and
               Kyehyun Kyung and
               Young{-}Hyun Jun and
               Kinam Kim},
  title     = {1.2V 1.6Gb/s 56nm 6F\({}^{\mbox{2}}\) 4Gb {DDR3} {SDRAM} with hybrid-I/O
               sense amplifier and segmented sub-array architecture},
  booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2009,
               Digest of Technical Papers, San Francisco, CA, USA, 8-12 February,
               2009},
  pages     = {128--129},
  year      = {2009},
  crossref  = {DBLP:conf/isscc/2009},
  url       = {https://doi.org/10.1109/ISSCC.2009.4977341},
  doi       = {10.1109/ISSCC.2009.4977341},
  timestamp = {Wed, 17 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isscc/MoonCLJHKJSSCSCKJK09},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/isscc/2019,
  title     = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2019,
               San Francisco, CA, USA, February 17-21, 2019},
  publisher = {{IEEE}},
  year      = {2019},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8656625},
  isbn      = {978-1-5386-8531-0},
  timestamp = {Tue, 12 Mar 2019 14:13:49 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/isscc/2019},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/isscc/2018,
  title     = {2018 {IEEE} International Solid-State Circuits Conference, {ISSCC}
               2018, San Francisco, CA, USA, February 11-15, 2018},
  publisher = {{IEEE}},
  year      = {2018},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8304413},
  isbn      = {978-1-5090-4940-0},
  timestamp = {Wed, 14 Mar 2018 15:12:33 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/isscc/2018},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/isscc/2017,
  title     = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC}
               2017, San Francisco, CA, USA, February 5-9, 2017},
  publisher = {{IEEE}},
  year      = {2017},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7866667},
  isbn      = {978-1-5090-3758-2},
  timestamp = {Fri, 10 Mar 2017 11:00:31 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/isscc/2017},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/isscc/2016,
  title     = {2016 {IEEE} International Solid-State Circuits Conference, {ISSCC}
               2016, San Francisco, CA, USA, January 31 - February 4, 2016},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7405163},
  isbn      = {978-1-4673-9466-6},
  timestamp = {Wed, 02 Mar 2016 13:33:32 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/isscc/2016},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/isscc/2015,
  title     = {2015 {IEEE} International Solid-State Circuits Conference, {ISSCC}
               2015, Digest of Technical Papers, San Francisco, CA, USA, February
               22-26, 2015},
  publisher = {{IEEE}},
  year      = {2015},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7054075},
  isbn      = {978-1-4799-6223-5},
  timestamp = {Tue, 24 Mar 2015 08:51:19 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/isscc/2015},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/isscc/2012,
  title     = {2012 {IEEE} International Solid-State Circuits Conference, {ISSCC}
               2012, San Francisco, CA, USA, February 19-23, 2012},
  publisher = {{IEEE}},
  year      = {2012},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6171933},
  isbn      = {978-1-4673-0376-7},
  timestamp = {Wed, 18 Apr 2012 15:00:33 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isscc/2012},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsic/2012,
  title     = {Symposium on {VLSI} Circuits, {VLSIC} 2012, Honolulu, HI, USA, June
               13-15, 2012},
  publisher = {{IEEE}},
  year      = {2012},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6235082},
  isbn      = {978-1-4673-0848-9},
  timestamp = {Wed, 16 Mar 2016 12:11:17 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/vlsic/2012},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/isscc/2011,
  title     = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2011,
               Digest of Technical Papers, San Francisco, CA, USA, 20-24 February,
               2011},
  publisher = {{IEEE}},
  year      = {2011},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5740653},
  isbn      = {978-1-61284-303-2},
  timestamp = {Fri, 30 Sep 2011 11:17:51 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isscc/2011},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/isscc/2010,
  title     = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2010,
               Digest of Technical Papers, San Francisco, CA, USA, 7-11 February,
               2010},
  publisher = {{IEEE}},
  year      = {2010},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5428240},
  isbn      = {978-1-4244-6033-5},
  timestamp = {Tue, 18 Oct 2011 15:16:07 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isscc/2010},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/isscc/2009,
  title     = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2009,
               Digest of Technical Papers, San Francisco, CA, USA, 8-12 February,
               2009},
  publisher = {{IEEE}},
  year      = {2009},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=4926119},
  isbn      = {978-1-4244-3458-9},
  timestamp = {Wed, 19 Oct 2011 12:56:48 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isscc/2009},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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