BibTeX records: Chien-Wei Lo

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@article{DBLP:journals/jolpe/DiBBBLLMNSS17,
  author       = {Jia Di and
                  Brent A. Bell and
                  William Bouillon and
                  John Brady and
                  Thao Le and
                  Chien{-}Wei Lo and
                  Liang Men and
                  Spencer Nelson and
                  Francis Sabado and
                  Andrew Suchanek},
  title        = {Recent Advances in Low Power Asynchronous Circuit Design},
  journal      = {J. Low Power Electron.},
  volume       = {13},
  number       = {3},
  pages        = {280--297},
  year         = {2017},
  url          = {https://doi.org/10.1166/jolpe.2017.1494},
  doi          = {10.1166/JOLPE.2017.1494},
  timestamp    = {Wed, 10 Apr 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jolpe/DiBBBLLMNSS17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/icicdt/CaleyLSD14,
  author       = {Landon Caley and
                  Chien{-}Wei Lo and
                  Francis Sabado and
                  Jia Di},
  title        = {A comparative analysis of 3D-IC partitioning schemes for asynchronous
                  circuits},
  booktitle    = {2014 {IEEE} International Conference on {IC} Design {\&} Technology,
                  {ICICDT} 2014, Austin, TX, USA, May 28-30, 2014},
  pages        = {1--4},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/ICICDT.2014.6838586},
  doi          = {10.1109/ICICDT.2014.6838586},
  timestamp    = {Wed, 16 Oct 2019 14:14:54 +0200},
  biburl       = {https://dblp.org/rec/conf/icicdt/CaleyLSD14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/ispass/WangLYC12,
  author       = {Po{-}Han Wang and
                  Chien{-}Wei Lo and
                  Chia{-}Lin Yang and
                  Yu{-}Jung Cheng},
  editor       = {Rajeev Balasubramonian and
                  Vijayalakshmi Srinivasan},
  title        = {A cycle-level {SIMT-GPU} simulation framework},
  booktitle    = {2012 {IEEE} International Symposium on Performance Analysis of Systems
                  {\&} Software, New Brunswick, NJ, USA, April 1-3, 2012},
  pages        = {114--115},
  publisher    = {{IEEE} Computer Society},
  year         = {2012},
  url          = {https://doi.org/10.1109/ISPASS.2012.6189213},
  doi          = {10.1109/ISPASS.2012.6189213},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/ispass/WangLYC12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}