BibTeX records: Rajeev Malik

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@article{DBLP:journals/ibmrd/FreemanCEGHLMMN15,
  author       = {Gregory Freeman and
                  Paul Chang and
                  E. R. Engbrecht and
                  K. J. Giewont and
                  David F. Hilscher and
                  M. Lagus and
                  Timothy J. McArdle and
                  B. Morgenfeld and
                  Shreesh Narasimha and
                  James P. Norum and
                  K. A. Nummy and
                  Paul C. Parries and
                  G. Wang and
                  Jonathan K. Winslow and
                  Paul D. Agnello and
                  Rajeev Malik},
  title        = {Performance-optimized gate-first 22-nm {SOI} technology with embedded
                  {DRAM}},
  journal      = {{IBM} J. Res. Dev.},
  volume       = {59},
  number       = {1},
  year         = {2015},
  url          = {https://doi.org/10.1147/JRD.2014.2380252},
  doi          = {10.1147/JRD.2014.2380252},
  timestamp    = {Fri, 03 Feb 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/ibmrd/FreemanCEGHLMMN15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/icicdt/JayaramanGZGHKF12,
  author       = {Balaji Jayaraman and
                  Sneha Gupta and
                  Yanli Zhang and
                  Puneet Goyal and
                  Herbert Ho and
                  Rishikesh Krishnan and
                  Sunfei Fang and
                  Sungjae Lee and
                  Douglas Daley and
                  Kevin McStay and
                  Bernhard Wunder and
                  John Barth and
                  Sadanand Deshpande and
                  Paul C. Parries and
                  Rajeev Malik and
                  Paul D. Agnello and
                  Scott R. Stiffler and
                  Subramanian S. Iyer},
  title        = {Performance analysis and modeling of deep trench decoupling capacitor
                  for 32 nm high-performance {SOI} processors and beyond},
  booktitle    = {{IEEE} International Conference on {IC} Design {\&} Technology,
                  {ICICDT} 2012, Austin, TX, USA, May 30 - June 1, 2012},
  pages        = {1--4},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/ICICDT.2012.6232872},
  doi          = {10.1109/ICICDT.2012.6232872},
  timestamp    = {Fri, 25 Feb 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/icicdt/JayaramanGZGHKF12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/cicc/ChanRIYMTYO05,
  author       = {Victor Chan and
                  Ken Rim and
                  Meikei Ieong and
                  Sam Yang and
                  Rajeev Malik and
                  Young Way Teh and
                  Min Yang and
                  Qiqing Ouyang},
  title        = {Strain for {CMOS} performance improvement},
  booktitle    = {Proceedings of the {IEEE} 2005 Custom Integrated Circuits Conference,
                  {CICC} 2005, DoubleTree Hotel, San Jose, California, USA, September
                  18-21, 2005},
  pages        = {667--674},
  publisher    = {{IEEE}},
  year         = {2005},
  url          = {https://doi.org/10.1109/CICC.2005.1568758},
  doi          = {10.1109/CICC.2005.1568758},
  timestamp    = {Mon, 15 Nov 2021 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/cicc/ChanRIYMTYO05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}