BibTeX records: Mengjie Mao

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@article{DBLP:journals/tcasI/LiuMBLC21,
  author       = {Xiaoxiao Liu and
                  Mengjie Mao and
                  Xiuyuan Bi and
                  Hai Helen Li and
                  Yiran Chen},
  title        = {Exploring Applications of {STT-RAM} in {GPU} Architectures},
  journal      = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
  volume       = {68},
  number       = {1},
  pages        = {238--249},
  year         = {2021},
  url          = {https://doi.org/10.1109/TCSI.2020.3031895},
  doi          = {10.1109/TCSI.2020.3031895},
  timestamp    = {Mon, 04 Jul 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tcasI/LiuMBLC21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jetc/LiMLLLWCL19,
  author       = {Bing Li and
                  Mengjie Mao and
                  Xiaoxiao Liu and
                  Tao Liu and
                  Zihao Liu and
                  Wujie Wen and
                  Yiran Chen and
                  Hai (Helen) Li},
  title        = {Thread Batching for High-performance Energy-efficient {GPU} Memory
                  Design},
  journal      = {{ACM} J. Emerg. Technol. Comput. Syst.},
  volume       = {15},
  number       = {4},
  pages        = {39:1--39:21},
  year         = {2019},
  url          = {https://doi.org/10.1145/3330152},
  doi          = {10.1145/3330152},
  timestamp    = {Mon, 04 Jul 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jetc/LiMLLLWCL19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1906-05922,
  author       = {Bing Li and
                  Mengjie Mao and
                  Xiaoxiao Liu and
                  Tao Liu and
                  Zihao Liu and
                  Wujie Wen and
                  Yiran Chen and
                  Hai Helen Li},
  title        = {Thread Batching for High-performance Energy-efficient {GPU} Memory
                  Design},
  journal      = {CoRR},
  volume       = {abs/1906.05922},
  year         = {2019},
  url          = {http://arxiv.org/abs/1906.05922},
  eprinttype    = {arXiv},
  eprint       = {1906.05922},
  timestamp    = {Mon, 04 Jul 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/corr/abs-1906-05922.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuMLWWCLWPG18,
  author       = {Zihao Liu and
                  Mengjie Mao and
                  Tao Liu and
                  Xue Wang and
                  Wujie Wen and
                  Yiran Chen and
                  Hai Li and
                  Danghui Wang and
                  Yukui Pei and
                  Ning Ge},
  title        = {TriZone: {A} Design of {MLC} {STT-RAM} Cache for Combined Performance,
                  Energy, and Reliability Optimizations},
  journal      = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
  volume       = {37},
  number       = {10},
  pages        = {1985--1998},
  year         = {2018},
  url          = {https://doi.org/10.1109/TCAD.2017.2783860},
  doi          = {10.1109/TCAD.2017.2783860},
  timestamp    = {Mon, 04 Jul 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tcad/LiuMLWWCLWPG18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/MaoWZCL17,
  author       = {Mengjie Mao and
                  Wujie Wen and
                  Yaojun Zhang and
                  Yiran Chen and
                  Hai Li},
  title        = {An Energy-Efficient {GPGPU} Register File Architecture Using Racetrack
                  Memory},
  journal      = {{IEEE} Trans. Computers},
  volume       = {66},
  number       = {9},
  pages        = {1478--1490},
  year         = {2017},
  url          = {https://doi.org/10.1109/TC.2017.2690855},
  doi          = {10.1109/TC.2017.2690855},
  timestamp    = {Mon, 04 Jul 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tc/MaoWZCL17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BiMWL17,
  author       = {Xiuyuan Bi and
                  Mengjie Mao and
                  Danghui Wang and
                  Hai Helen Li},
  title        = {Cross-Layer Optimization for Multilevel Cell {STT-RAM} Caches},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {25},
  number       = {6},
  pages        = {1807--1820},
  year         = {2017},
  url          = {https://doi.org/10.1109/TVLSI.2017.2665543},
  doi          = {10.1109/TVLSI.2017.2665543},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/BiMWL17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/LiuMLLWJBWYLC16,
  author       = {Xiaoxiao Liu and
                  Mengjie Mao and
                  Beiye Liu and
                  Boxun Li and
                  Yu Wang and
                  Hao Jiang and
                  Mark Barnell and
                  Qing Wu and
                  Jianhua Joshua Yang and
                  Hai Li and
                  Yiran Chen},
  title        = {Harmonica: {A} Framework of Heterogeneous Computing Systems With Memristor-Based
                  Neuromorphic Computing Accelerators},
  journal      = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
  volume       = {63-I},
  number       = {5},
  pages        = {617--628},
  year         = {2016},
  url          = {https://doi.org/10.1109/TCSI.2016.2529279},
  doi          = {10.1109/TCSI.2016.2529279},
  timestamp    = {Sun, 12 Nov 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tcas/LiuMLLWJBWYLC16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/MaoWLHWCL16,
  author       = {Mengjie Mao and
                  Wujie Wen and
                  Xiaoxiao Liu and
                  Jingtong Hu and
                  Danghui Wang and
                  Yiran Chen and
                  Hai Li},
  title        = {{TEMP:} thread batch enabled memory partitioning for {GPU}},
  booktitle    = {Proceedings of the 53rd Annual Design Automation Conference, {DAC}
                  2016, Austin, TX, USA, June 5-9, 2016},
  pages        = {65:1--65:6},
  publisher    = {{ACM}},
  year         = {2016},
  url          = {https://doi.org/10.1145/2897937.2898103},
  doi          = {10.1145/2897937.2898103},
  timestamp    = {Mon, 04 Jul 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/dac/MaoWLHWCL16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/WangMEWLC16,
  author       = {Xue Wang and
                  Mengjie Mao and
                  Enes Eken and
                  Wujie Wen and
                  Hai Li and
                  Yiran Chen},
  editor       = {Luca Fanucci and
                  J{\"{u}}rgen Teich},
  title        = {Sliding Basket: An adaptive {ECC} scheme for runtime write failure
                  suppression of {STT-RAM} cache},
  booktitle    = {2016 Design, Automation {\&} Test in Europe Conference {\&}
                  Exhibition, {DATE} 2016, Dresden, Germany, March 14-18, 2016},
  pages        = {762--767},
  publisher    = {{IEEE}},
  year         = {2016},
  url          = {https://ieeexplore.ieee.org/document/7459409/},
  timestamp    = {Mon, 04 Jul 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/date/WangMEWLC16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/WenMLCPG16,
  author       = {Wujie Wen and
                  Mengjie Mao and
                  Hai Li and
                  Yiran Chen and
                  Yukui Pei and
                  Ning Ge},
  editor       = {Luca Fanucci and
                  J{\"{u}}rgen Teich},
  title        = {A holistic tri-region {MLC} {STT-RAM} design with combined performance,
                  energy, and reliability optimizations},
  booktitle    = {2016 Design, Automation {\&} Test in Europe Conference {\&}
                  Exhibition, {DATE} 2016, Dresden, Germany, March 14-18, 2016},
  pages        = {1285--1290},
  publisher    = {{IEEE}},
  year         = {2016},
  url          = {https://ieeexplore.ieee.org/document/7459508/},
  timestamp    = {Mon, 04 Jul 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/date/WenMLCPG16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/LiLMLCLW16,
  author       = {Sicheng Li and
                  Xiaoxiao Liu and
                  Mengjie Mao and
                  Hai (Helen) Li and
                  Yiran Chen and
                  Boxun Li and
                  Yu Wang},
  title        = {Heterogeneous systems with reconfigurable neuromorphic computing accelerators},
  booktitle    = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2016,
                  Montr{\'{e}}al, QC, Canada, May 22-25, 2016},
  pages        = {125--128},
  publisher    = {{IEEE}},
  year         = {2016},
  url          = {https://doi.org/10.1109/ISCAS.2016.7527186},
  doi          = {10.1109/ISCAS.2016.7527186},
  timestamp    = {Mon, 04 Jul 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/iscas/LiLMLCLW16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/LiuMBLC15,
  author       = {Xiaoxiao Liu and
                  Mengjie Mao and
                  Xiuyuan Bi and
                  Hai Li and
                  Yiran Chen},
  title        = {An efficient STT-RAM-based register file in {GPU} architectures},
  booktitle    = {The 20th Asia and South Pacific Design Automation Conference, {ASP-DAC}
                  2015, Chiba, Japan, January 19-22, 2015},
  pages        = {490--495},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/ASPDAC.2015.7059054},
  doi          = {10.1109/ASPDAC.2015.7059054},
  timestamp    = {Mon, 04 Jul 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/aspdac/LiuMBLC15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/LiuMLLCLWJBWY15,
  author       = {Xiaoxiao Liu and
                  Mengjie Mao and
                  Beiye Liu and
                  Hai Li and
                  Yiran Chen and
                  Boxun Li and
                  Yu Wang and
                  Hao Jiang and
                  Mark Barnell and
                  Qing Wu and
                  Jianhua Joshua Yang},
  title        = {{RENO:} a high-efficient reconfigurable neuromorphic computing accelerator
                  design},
  booktitle    = {Proceedings of the 52nd Annual Design Automation Conference, San Francisco,
                  CA, USA, June 7-11, 2015},
  pages        = {66:1--66:6},
  publisher    = {{ACM}},
  year         = {2015},
  url          = {https://doi.org/10.1145/2744769.2744900},
  doi          = {10.1145/2744769.2744900},
  timestamp    = {Sun, 12 Nov 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/dac/LiuMLLCLWJBWY15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/MaoHCL15,
  author       = {Mengjie Mao and
                  Jingtong Hu and
                  Yiran Chen and
                  Hai Li},
  title        = {{VWS:} a versatile warp scheduler for exploring diverse cache localities
                  of {GPGPU} applications},
  booktitle    = {Proceedings of the 52nd Annual Design Automation Conference, San Francisco,
                  CA, USA, June 7-11, 2015},
  pages        = {83:1--83:6},
  publisher    = {{ACM}},
  year         = {2015},
  url          = {https://doi.org/10.1145/2744769.2744931},
  doi          = {10.1145/2744769.2744931},
  timestamp    = {Mon, 04 Jul 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/dac/MaoHCL15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/LiLLMCWQ15,
  author       = {Hai Li and
                  Beiye Liu and
                  Xiaoxiao Liu and
                  Mengjie Mao and
                  Yiran Chen and
                  Qing Wu and
                  Qinru Qiu},
  title        = {The applications of memristor devices in next-generation cortical
                  processor designs},
  booktitle    = {2015 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
                  2015, Lisbon, Portugal, May 24-27, 2015},
  pages        = {17--20},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/ISCAS.2015.7168559},
  doi          = {10.1109/ISCAS.2015.7168559},
  timestamp    = {Tue, 28 Nov 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/iscas/LiLLMCWQ15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/MaoSLJC14,
  author       = {Mengjie Mao and
                  Guangyu Sun and
                  Yong Li and
                  Alex K. Jones and
                  Yiran Chen},
  title        = {Prefetching techniques for {STT-RAM} based last-level cache in {CMP}
                  systems},
  booktitle    = {19th Asia and South Pacific Design Automation Conference, {ASP-DAC}
                  2014, Singapore, January 20-23, 2014},
  pages        = {67--72},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/ASPDAC.2014.6742868},
  doi          = {10.1109/ASPDAC.2014.6742868},
  timestamp    = {Tue, 21 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/aspdac/MaoSLJC14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/WenZMC14,
  author       = {Wujie Wen and
                  Yaojun Zhang and
                  Mengjie Mao and
                  Yiran Chen},
  title        = {State-Restrict {MLC} {STT-RAM} Designs for High-Reliable High-Performance
                  Memory System},
  booktitle    = {The 51st Annual Design Automation Conference 2014, {DAC} '14, San
                  Francisco, CA, USA, June 1-5, 2014},
  pages        = {35:1--35:6},
  publisher    = {{ACM}},
  year         = {2014},
  url          = {https://doi.org/10.1145/2593069.2593220},
  doi          = {10.1145/2593069.2593220},
  timestamp    = {Mon, 04 Jul 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/dac/WenZMC14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/MaoWZCL14,
  author       = {Mengjie Mao and
                  Wujie Wen and
                  Yaojun Zhang and
                  Yiran Chen and
                  Hai (Helen) Li},
  title        = {Exploration of {GPGPU} Register File Architecture Using Domain-wall-shift-write
                  based Racetrack Memory},
  booktitle    = {The 51st Annual Design Automation Conference 2014, {DAC} '14, San
                  Francisco, CA, USA, June 1-5, 2014},
  pages        = {196:1--196:6},
  publisher    = {{ACM}},
  year         = {2014},
  url          = {https://doi.org/10.1145/2593069.2593137},
  doi          = {10.1145/2593069.2593137},
  timestamp    = {Mon, 04 Jul 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/dac/MaoWZCL14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpec/LiuMLCJYWB14,
  author       = {Xiaoxiao Liu and
                  Mengjie Mao and
                  Hai Li and
                  Yiran Chen and
                  Hao Jiang and
                  J. Joshua Yang and
                  Qing Wu and
                  Mark Barnell},
  title        = {A heterogeneous computing system with memristor-based neuromorphic
                  accelerators},
  booktitle    = {{IEEE} High Performance Extreme Computing Conference, {HPEC} 2014,
                  Waltham, MA, USA, September 9-11, 2014},
  pages        = {1--6},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/HPEC.2014.7040986},
  doi          = {10.1109/HPEC.2014.7040986},
  timestamp    = {Mon, 04 Jul 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/hpec/LiuMLCJYWB14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isicir/LiLMCWB14,
  author       = {Hai Li and
                  Xiaoxiao Liu and
                  Mengjie Mao and
                  Yiran Chen and
                  Qing Wu and
                  Mark Barnell},
  title        = {Neuromorphic hardware acceleration enabled by emerging technologies
                  (Invited paper)},
  booktitle    = {2014 International Symposium on Integrated Circuits (ISIC), Singapore,
                  December 10-12, 2014},
  pages        = {124--127},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/ISICIR.2014.7029530},
  doi          = {10.1109/ISICIR.2014.7029530},
  timestamp    = {Mon, 04 Jul 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isicir/LiLMCWB14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/LiHLMLD14,
  author       = {Hai Li and
                  Miao Hu and
                  Xiaoxiao Liu and
                  Mengjie Mao and
                  Chuandong Li and
                  Shukai Duan},
  editor       = {Kaijian Shi and
                  Thomas B{\"{u}}chner and
                  Danella Zhao and
                  Ramalingam Sridhar},
  title        = {Emerging memristor technology enabled next generation cortical processor},
  booktitle    = {27th {IEEE} International System-on-Chip Conference, {SOCC} 2014,
                  Las Vegas, NV, USA, September 2-5, 2014},
  pages        = {377--382},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/SOCC.2014.6948958},
  doi          = {10.1109/SOCC.2014.6948958},
  timestamp    = {Tue, 21 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/socc/LiHLMLD14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/MaoLJC13,
  author       = {Mengjie Mao and
                  Hai (Helen) Li and
                  Alex K. Jones and
                  Yiran Chen},
  editor       = {Jos{\'{e}} Luis Ayala and
                  Alex K. Jones and
                  Patrick H. Madden and
                  Ayse K. Coskun},
  title        = {Coordinating prefetching and {STT-RAM} based last-level cache management
                  for multicore systems},
  booktitle    = {Great Lakes Symposium on {VLSI} 2013 (part of ECRC), GLSVLSI'13, Paris,
                  France, May 2-4, 2013},
  pages        = {55--60},
  publisher    = {{ACM}},
  year         = {2013},
  url          = {https://doi.org/10.1145/2483028.2483060},
  doi          = {10.1145/2483028.2483060},
  timestamp    = {Tue, 21 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/glvlsi/MaoLJC13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/WenMZKWC13,
  author       = {Wujie Wen and
                  Mengjie Mao and
                  Xiaochun Zhu and
                  Seung H. Kang and
                  Danghui Wang and
                  Yiran Chen},
  editor       = {J{\"{o}}rg Henkel},
  title        = {{CD-ECC:} content-dependent error correction codes for combating asymmetric
                  nonvolatile memory operation errors},
  booktitle    = {The {IEEE/ACM} International Conference on Computer-Aided Design,
                  ICCAD'13, San Jose, CA, USA, November 18-21, 2013},
  pages        = {1--8},
  publisher    = {{IEEE}},
  year         = {2013},
  url          = {https://doi.org/10.1109/ICCAD.2013.6691090},
  doi          = {10.1109/ICCAD.2013.6691090},
  timestamp    = {Mon, 04 Jul 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/iccad/WenMZKWC13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/BiMWL13,
  author       = {Xiuyuan Bi and
                  Mengjie Mao and
                  Danghui Wang and
                  Hai Li},
  editor       = {J{\"{o}}rg Henkel},
  title        = {Unleashing the potential of {MLC} {STT-RAM} caches},
  booktitle    = {The {IEEE/ACM} International Conference on Computer-Aided Design,
                  ICCAD'13, San Jose, CA, USA, November 18-21, 2013},
  pages        = {429--436},
  publisher    = {{IEEE}},
  year         = {2013},
  url          = {https://doi.org/10.1109/ICCAD.2013.6691153},
  doi          = {10.1109/ICCAD.2013.6691153},
  timestamp    = {Fri, 02 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/iccad/BiMWL13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ACISicis/MaoASLDWZ12,
  author       = {Mengjie Mao and
                  Hong An and
                  Tao Sun and
                  Qi Li and
                  Bobin Deng and
                  Xuechao Wei and
                  Junrui Zhou},
  editor       = {Huaikou Miao and
                  Roger Y. Lee and
                  Hongwei Zeng and
                  Jongmoon Baik},
  title        = {Distributed Control Independence for Composable Multi-processors},
  booktitle    = {2012 {IEEE/ACIS} 11th International Conference on Computer and Information
                  Science, Shanghai, China, May 30 - June 1, 2012},
  pages        = {124--129},
  publisher    = {{IEEE} Computer Society},
  year         = {2012},
  url          = {https://doi.org/10.1109/ICIS.2012.45},
  doi          = {10.1109/ICIS.2012.45},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/ACISicis/MaoASLDWZ12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ACISicis/DengALLM12,
  author       = {Bobin Deng and
                  Hong An and
                  Qi Li and
                  Gongming Li and
                  Mengjie Mao},
  editor       = {Huaikou Miao and
                  Roger Y. Lee and
                  Hongwei Zeng and
                  Jongmoon Baik},
  title        = {Value Predicted LogSPoTM: Improve the Parallesim of Thread Level System
                  by Using a Value Predictor},
  booktitle    = {2012 {IEEE/ACIS} 11th International Conference on Computer and Information
                  Science, Shanghai, China, May 30 - June 1, 2012},
  pages        = {130--135},
  publisher    = {{IEEE} Computer Society},
  year         = {2012},
  url          = {https://doi.org/10.1109/ICIS.2012.116},
  doi          = {10.1109/ICIS.2012.116},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/ACISicis/DengALLM12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ics/MaoADSWZH12,
  author       = {Mengjie Mao and
                  Hong An and
                  Bobin Deng and
                  Tao Sun and
                  Xuechao Wei and
                  Wei Zhou and
                  Wenting Han},
  editor       = {Utpal Banerjee and
                  Kyle A. Gallivan and
                  Gianfranco Bilardi and
                  Manolis Katevenis},
  title        = {Distributed replay protocol for distributed uniprocessors},
  booktitle    = {International Conference on Supercomputing, ICS'12, Venice, Italy,
                  June 25-29, 2012},
  pages        = {3--14},
  publisher    = {{ACM}},
  year         = {2012},
  url          = {https://doi.org/10.1145/2304576.2304580},
  doi          = {10.1145/2304576.2304580},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/ics/MaoADSWZH12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/pdcat/SunARMLXL10,
  author       = {Tao Sun and
                  Hong An and
                  Yongqing Ren and
                  Mengjie Mao and
                  Yang Liu and
                  Mu Xu and
                  Qi Li},
  title        = {{FACRA:} Flexible-Core Architecture Chip Resource Abstractor},
  booktitle    = {2010 International Conference on Parallel and Distributed Computing,
                  Applications and Technologies, {PDCAT} 2010, Wuhan, China, 8-11 December,
                  2010},
  pages        = {440--447},
  publisher    = {{IEEE} Computer Society},
  year         = {2010},
  url          = {https://doi.org/10.1109/PDCAT.2010.22},
  doi          = {10.1109/PDCAT.2010.22},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/pdcat/SunARMLXL10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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