BibTeX records: Hidenari Nakashima

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@article{DBLP:journals/ieicet/KanamotoOFTKHSTNMSH10,
  author       = {Toshiki Kanamoto and
                  Takaaki Okumura and
                  Katsuhiro Furukawa and
                  Hiroshi Takafuji and
                  Atsushi Kurokawa and
                  Koutaro Hachiya and
                  Tsuyoshi Sakata and
                  Masakazu Tanaka and
                  Hidenari Nakashima and
                  Hiroo Masuda and
                  Takashi Sato and
                  Masanori Hashimoto},
  title        = {Impact of Self-Heating in Wire Interconnection on Timing},
  journal      = {{IEICE} Trans. Electron.},
  volume       = {93-C},
  number       = {3},
  pages        = {388--392},
  year         = {2010},
  url          = {https://doi.org/10.1587/transele.E93.C.388},
  doi          = {10.1587/TRANSELE.E93.C.388},
  timestamp    = {Mon, 03 Jan 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/ieicet/KanamotoOFTKHSTNMSH10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ieicet/OkumuraKMKHTNOSS09,
  author       = {Takaaki Okumura and
                  Atsushi Kurokawa and
                  Hiroo Masuda and
                  Toshiki Kanamoto and
                  Masanori Hashimoto and
                  Hiroshi Takafuji and
                  Hidenari Nakashima and
                  Nobuto Ono and
                  Tsuyoshi Sakata and
                  Takashi Sato},
  title        = {Improvement in Computational Accuracy of Output Transition Time Variation
                  Considering Threshold Voltage Variations},
  journal      = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
  volume       = {92-A},
  number       = {4},
  pages        = {990--997},
  year         = {2009},
  url          = {https://doi.org/10.1587/transfun.E92.A.990},
  doi          = {10.1587/TRANSFUN.E92.A.990},
  timestamp    = {Mon, 03 Jan 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/ieicet/OkumuraKMKHTNOSS09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ieicet/SakataOKNMSHHFTTK09,
  author       = {Tsuyoshi Sakata and
                  Takaaki Okumura and
                  Atsushi Kurokawa and
                  Hidenari Nakashima and
                  Hiroo Masuda and
                  Takashi Sato and
                  Masanori Hashimoto and
                  Koutaro Hachiya and
                  Katsuhiro Furukawa and
                  Masakazu Tanaka and
                  Hiroshi Takafuji and
                  Toshiki Kanamoto},
  title        = {An Approach for Reducing Leakage Current Variation due to Manufacturing
                  Variability},
  journal      = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
  volume       = {92-A},
  number       = {12},
  pages        = {3016--3023},
  year         = {2009},
  url          = {https://doi.org/10.1587/transfun.E92.A.3016},
  doi          = {10.1587/TRANSFUN.E92.A.3016},
  timestamp    = {Mon, 03 Jan 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/ieicet/SakataOKNMSHHFTTK09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ieicet/HachiyaONSG07,
  author       = {Koutaro Hachiya and
                  Takayuki Ohshima and
                  Hidenari Nakashima and
                  Masaaki Soda and
                  Satoshi Goto},
  title        = {Fast Methods to Estimate Clock Jitter due to Power Supply Noise},
  journal      = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
  volume       = {90-A},
  number       = {4},
  pages        = {741--747},
  year         = {2007},
  url          = {https://doi.org/10.1093/ietfec/e90-a.4.741},
  doi          = {10.1093/IETFEC/E90-A.4.741},
  timestamp    = {Sat, 11 Apr 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ieicet/HachiyaONSG07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ieicet/KobayashiOSINOH07,
  author       = {Hiroyuki Kobayashi and
                  Nobuto Ono and
                  Takashi Sato and
                  Jiro Iwai and
                  Hidenari Nakashima and
                  Takaaki Okumura and
                  Masanori Hashimoto},
  title        = {Proposal of Metrics for {SSTA} Accuracy Evaluation},
  journal      = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
  volume       = {90-A},
  number       = {4},
  pages        = {808--814},
  year         = {2007},
  url          = {https://doi.org/10.1093/ietfec/e90-a.4.808},
  doi          = {10.1093/IETFEC/E90-A.4.808},
  timestamp    = {Mon, 03 Jan 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/ieicet/KobayashiOSINOH07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ieicet/NakashimaIOM05,
  author       = {Hidenari Nakashima and
                  Junpei Inoue and
                  Kenichi Okada and
                  Kazuya Masu},
  title        = {Circuit Performance Prediction Considering Core Utilization with Interconnect
                  Length Distribution Model},
  journal      = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
  volume       = {88-A},
  number       = {12},
  pages        = {3358--3366},
  year         = {2005},
  url          = {https://doi.org/10.1093/ietfec/e88-a.12.3358},
  doi          = {10.1093/IETFEC/E88-A.12.3358},
  timestamp    = {Sat, 11 Apr 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ieicet/NakashimaIOM05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ieicet/NakashimaTIOM05,
  author       = {Hidenari Nakashima and
                  Naohiro Takagi and
                  Junpei Inoue and
                  Kenichi Okada and
                  Kazuya Masu},
  title        = {Evaluation of {X} Architecture Using Interconnect Length Distribution},
  journal      = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
  volume       = {88-A},
  number       = {12},
  pages        = {3437--3444},
  year         = {2005},
  url          = {https://doi.org/10.1093/ietfec/e88-a.12.3437},
  doi          = {10.1093/IETFEC/E88-A.12.3437},
  timestamp    = {Sat, 11 Apr 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ieicet/NakashimaTIOM05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ieicet/KyogokuINUOM05,
  author       = {Takanori Kyogoku and
                  Junpei Inoue and
                  Hidenari Nakashima and
                  Takumi Uezono and
                  Kenichi Okada and
                  Kazuya Masu},
  title        = {Wire Length Distribution Model for System {LSI}},
  journal      = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
  volume       = {88-A},
  number       = {12},
  pages        = {3445--3452},
  year         = {2005},
  url          = {https://doi.org/10.1093/ietfec/e88-a.12.3445},
  doi          = {10.1093/IETFEC/E88-A.12.3445},
  timestamp    = {Sat, 11 Apr 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ieicet/KyogokuINUOM05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isvlsi/KyogokuINUOM05,
  author       = {Takanori Kyogoku and
                  Junpei Inoue and
                  Hidenari Nakashima and
                  Takumi Uezono and
                  Kenichi Okada and
                  Kazuya Masu},
  title        = {Wire Length Distribution Model Considering Core Utilization for System
                  on Chip},
  booktitle    = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
                  2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
                  {USA}},
  pages        = {276--277},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISVLSI.2005.76},
  doi          = {10.1109/ISVLSI.2005.76},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isvlsi/KyogokuINUOM05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/date/NakashimaIOM04,
  author       = {Hidenari Nakashima and
                  Junpei Inoue and
                  Kenichi Okada and
                  Kazuya Masu},
  title        = {{ULSI} Interconnect Length Distribution Model Considering Core Utilization},
  booktitle    = {2004 Design, Automation and Test in Europe Conference and Exposition
                  {(DATE} 2004), 16-20 February 2004, Paris, France},
  pages        = {1210--1217},
  publisher    = {{IEEE} Computer Society},
  year         = {2004},
  url          = {https://doi.org/10.1109/DATE.2004.1269057},
  doi          = {10.1109/DATE.2004.1269057},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/date/NakashimaIOM04.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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