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ORCIDBibTeX records: Maurizio Palesi
@article{DBLP:journals/tjs/TangRP24,
author = {Minghua Tang and
Enrico Russo and
Maurizio Palesi},
title = {Correction to: The position-based compression techniques for {DNN}
model},
journal = {J. Supercomput.},
volume = {80},
number = {1},
pages = {1365},
year = {2024},
url = {https://doi.org/10.1007/s11227-023-05514-7},
doi = {10.1007/S11227-023-05514-7},
timestamp = {Fri, 19 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tjs/TangRP24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2403-00766,
author = {Enrico Russo and
Francesco Giulio Blanco and
Maurizio Palesi and
Giuseppe Ascia and
Davide Patti and
Vincenzo Catania},
title = {Towards Fair and Firm Real-Time Scheduling in {DNN} Multi-Tenant Multi-Accelerator
Systems via Reinforcement Learning},
journal = {CoRR},
volume = {abs/2403.00766},
year = {2024},
url = {https://doi.org/10.48550/arXiv.2403.00766},
doi = {10.48550/ARXIV.2403.00766},
eprinttype = {arXiv},
eprint = {2403.00766},
timestamp = {Tue, 02 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2403-00766.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/AiosaPS23,
author = {Grazia Veronica Aiosa and
Maurizio Palesi and
Francesca Sapuppo},
title = {EXplainable {AI} for Decision Support to Obesity Comorbidities Diagnosis},
journal = {{IEEE} Access},
volume = {11},
pages = {107767--107782},
year = {2023},
url = {https://doi.org/10.1109/ACCESS.2023.3320057},
doi = {10.1109/ACCESS.2023.3320057},
timestamp = {Sat, 14 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/access/AiosaPS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iotj/RussoPPMAC23,
author = {Enrico Russo and
Maurizio Palesi and
Davide Patti and
Salvatore Monteleone and
Giuseppe Ascia and
Vincenzo Catania},
title = {Multiobjective End-to-End Design Space Exploration of Parameterized
{DNN} Accelerators},
journal = {{IEEE} Internet Things J.},
volume = {10},
number = {2},
pages = {1800--1812},
year = {2023},
url = {https://doi.org/10.1109/JIOT.2022.3209401},
doi = {10.1109/JIOT.2022.3209401},
timestamp = {Tue, 31 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/iotj/RussoPPMAC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tjs/TangRP23,
author = {Minghua Tang and
Enrico Russo and
Maurizio Palesi},
title = {The position-based compression techniques for {DNN} model},
journal = {J. Supercomput.},
volume = {79},
number = {15},
pages = {17445--17474},
year = {2023},
url = {https://doi.org/10.1007/s11227-023-05339-4},
doi = {10.1007/S11227-023-05339-4},
timestamp = {Sun, 10 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tjs/TangRP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cf/RussoPAPMC23,
author = {Enrico Russo and
Maurizio Palesi and
Giuseppe Ascia and
Davide Patti and
Salvatore Monteleone and
Vincenzo Catania},
editor = {Andrea Bartolini and
Kristian F. D. Rietveld and
Catherine D. Schuman and
Jose Moreira},
title = {Memory-Aware {DNN} Algorithm-Hardware Mapping via Integer Linear Programming},
booktitle = {Proceedings of the 20th {ACM} International Conference on Computing
Frontiers, {CF} 2023, Bologna, Italy, May 9-11, 2023},
pages = {134--143},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3587135.3592206},
doi = {10.1145/3587135.3592206},
timestamp = {Sat, 30 Sep 2023 09:36:30 +0200},
biburl = {https://dblp.org/rec/conf/cf/RussoPAPMC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/eScience/AiosaPSX23,
author = {Grazia Veronica Aiosa and
Maurizio Palesi and
Francesca Sapuppo and
Maria Gabriella Xibilia},
title = {Explainable AI-Based Clinical Decision Support System for Obesity
Comorbidity Analysis},
booktitle = {19th {IEEE} International Conference on e-Science, e-Science 2023,
Limassol, Cyprus, October 9-13, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/e-Science58273.2023.10254948},
doi = {10.1109/E-SCIENCE58273.2023.10254948},
timestamp = {Sat, 14 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/eScience/AiosaPSX23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/PalesiRDJ23,
author = {Maurizio Palesi and
Enrico Russo and
Abhijit Das and
John Jose},
title = {Wireless enabled Inter-Chiplet Communication in {DNN} Hardware Accelerators},
booktitle = {{IEEE} International Parallel and Distributed Processing Symposium,
{IPDPS} 2023 - Workshops, St. Petersburg, FL, USA, May 15-19, 2023},
pages = {477--483},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/IPDPSW59300.2023.00081},
doi = {10.1109/IPDPSW59300.2023.00081},
timestamp = {Wed, 09 Aug 2023 16:25:12 +0200},
biburl = {https://dblp.org/rec/conf/ipps/PalesiRDJ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/AlarconASBCBPBL23,
author = {Eduard Alarc{\'{o}}n and
Sergi Abadal and
Fabio Sebastiano and
Masoud Babaie and
Edoardo Charbon and
Peter Haring Bol{\'{\i}}var and
Maurizio Palesi and
Elena Blokhina and
Dirk Leipold and
Robert Bogdan Staszewski and
Artur Garc{\'{\i}}a{-}S{\'{a}}ez and
Carmen G. Almud{\'{e}}ver},
title = {Scalable multi-chip quantum architectures enabled by cryogenic hybrid
wireless/quantum-coherent network-in-package},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2023,
Monterey, CA, USA, May 21-25, 2023},
pages = {1--5},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISCAS46773.2023.10181857},
doi = {10.1109/ISCAS46773.2023.10181857},
timestamp = {Mon, 31 Jul 2023 09:04:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/AlarconASBCBPBL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/most/RafiquePPC23,
author = {Hamaad Rafique and
Davide Patti and
Maurizio Palesi and
Vincenzo Catania},
title = {m-BMC: Exploration of Magnetic Field Measurements for Indoor Positioning
Using mini-Batch Magnetometer Calibration},
booktitle = {{IEEE} International Conference on Mobility, Operations, Services
and Technologies, {MOST} 2023, Detroit, MI, USA, May 17-19, 2023},
pages = {55--61},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/MOST57249.2023.00014},
doi = {10.1109/MOST57249.2023.00014},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/most/RafiquePPC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2303-14008,
author = {Eduard Alarc{\'{o}}n and
Sergi Abadal and
Fabio Sebastiano and
Masoud Babaie and
Edoardo Charbon and
Peter Haring Bol{\'{\i}}var and
Maurizio Palesi and
Elena Blokhina and
Dirk Leipold and
Robert Bogdan Staszewski and
Artur Garc{\'{\i}}a{-}S{\'{a}}ez and
Carmen G. Almud{\'{e}}ver},
title = {Scalable multi-chip quantum architectures enabled by cryogenic hybrid
wireless/quantum-coherent network-in-package},
journal = {CoRR},
volume = {abs/2303.14008},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2303.14008},
doi = {10.48550/ARXIV.2303.14008},
eprinttype = {arXiv},
eprint = {2303.14008},
timestamp = {Thu, 13 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2303-14008.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2306-15552,
author = {Cristina Silvano and
Daniele Ielmini and
Fabrizio Ferrandi and
Leandro Fiorin and
Serena Curzel and
Luca Benini and
Francesco Conti and
Angelo Garofalo and
Cristian Zambelli and
Enrico Calore and
Sebastiano Fabio Schifano and
Maurizio Palesi and
Giuseppe Ascia and
Davide Patti and
Stefania Perri and
Nicola Petra and
Davide De Caro and
Luciano Lavagno and
Teodoro Urso and
Valeria Cardellini and
Gian Carlo Cardarilli and
Robert Birke},
title = {A Survey on Deep Learning Hardware Accelerators for Heterogeneous
{HPC} Platforms},
journal = {CoRR},
volume = {abs/2306.15552},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2306.15552},
doi = {10.48550/ARXIV.2306.15552},
eprinttype = {arXiv},
eprint = {2306.15552},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2306-15552.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2311-17815,
author = {Fabrizio Ferrandi and
Serena Curzel and
Leandro Fiorin and
Daniele Ielmini and
Cristina Silvano and
Francesco Conti and
Alessio Burrello and
Francesco Barchi and
Luca Benini and
Luciano Lavagno and
Teodoro Urso and
Enrico Calore and
Sebastiano Fabio Schifano and
Cristian Zambelli and
Maurizio Palesi and
Giuseppe Ascia and
Enrico Russo and
Nicola Petra and
Davide De Caro and
Gennaro Di Meo and
Valeria Cardellini and
Salvatore Filippone and
Francesco Lo Presti and
Francesco Silvestri and
Paolo Palazzari and
Stefania Perri},
title = {A Survey on Design Methodologies for Accelerating Deep Learning on
Heterogeneous Architectures},
journal = {CoRR},
volume = {abs/2311.17815},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2311.17815},
doi = {10.48550/ARXIV.2311.17815},
eprinttype = {arXiv},
eprint = {2311.17815},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2311-17815.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cem/DasKJP22,
author = {Abhijit Das and
Abhishek Kumar and
John Jose and
Maurizio Palesi},
title = {Revising NoC in Future Multicore-Based Consumer Electronics for Performance},
journal = {{IEEE} Consumer Electron. Mag.},
volume = {11},
number = {3},
pages = {79--86},
year = {2022},
url = {https://doi.org/10.1109/MCE.2021.3062001},
doi = {10.1109/MCE.2021.3062001},
timestamp = {Wed, 18 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/cem/DasKJP22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/ChenYPPCH0Z022,
author = {Chixiao Chen and
Jieming Yin and
Yarui Peng and
Maurizio Palesi and
Wenxu Cao and
Letian Huang and
Amit Kumar Singh and
Haocong Zhi and
Xiaohang Wang},
title = {Design Challenges of Intrachiplet and Interchiplet Interconnection},
journal = {{IEEE} Des. Test},
volume = {39},
number = {6},
pages = {99--109},
year = {2022},
url = {https://doi.org/10.1109/MDAT.2022.3203005},
doi = {10.1109/MDAT.2022.3203005},
timestamp = {Sun, 13 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/dt/ChenYPPCH0Z022.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iotj/RussoPMPMAC22,
author = {Enrico Russo and
Maurizio Palesi and
Salvatore Monteleone and
Davide Patti and
Andrea Mineo and
Giuseppe Ascia and
Vincenzo Catania},
title = {{DNN} Model Compression for IoT Domain-Specific Hardware Accelerators},
journal = {{IEEE} Internet Things J.},
volume = {9},
number = {9},
pages = {6650--6662},
year = {2022},
url = {https://doi.org/10.1109/JIOT.2021.3111723},
doi = {10.1109/JIOT.2021.3111723},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/iotj/RussoPMPMAC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/RussoPMPAC22,
author = {Enrico Russo and
Maurizio Palesi and
Salvatore Monteleone and
Davide Patti and
Giuseppe Ascia and
Vincenzo Catania},
editor = {Cristiana Bolchini and
Ingrid Verbauwhede and
Ioana Vatajelu},
title = {{MEDEA:} {A} Multi-objective Evolutionary Approach to {DNN} Hardware
Mapping},
booktitle = {2022 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2022, Antwerp, Belgium, March 14-23, 2022},
pages = {226--231},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.23919/DATE54114.2022.9774747},
doi = {10.23919/DATE54114.2022.9774747},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/RussoPMPAC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/RussoPPLMAC22,
author = {Enrico Russo and
Maurizio Palesi and
Davide Patti and
Habiba Lahdhiri and
Salvatore Monteleone and
Giuseppe Ascia and
Vincenzo Catania},
title = {Combined Application of Approximate Computing Techniques in {DNN}
Hardware Accelerators},
booktitle = {{IEEE} International Parallel and Distributed Processing Symposium,
{IPDPS} Workshops 2022, Lyon, France, May 30 - June 3, 2022},
pages = {16--23},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/IPDPSW55747.2022.00013},
doi = {10.1109/IPDPSW55747.2022.00013},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ipps/RussoPPLMAC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/meco/RussoPMPLAC22,
author = {Enrico Russo and
Maurizio Palesi and
Salvatore Monteleone and
Davide Patti and
Habiba Lahdhiri and
Giuseppe Ascia and
Vincenzo Catania},
title = {Exploiting the Approximate Computing Paradigm with {DNN} Hardware
Accelerators},
booktitle = {11th Mediterranean Conference on Embedded Computing, {MECO} 2022,
Budva, Montenegro, June 7-10, 2022},
pages = {1--4},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/MECO55406.2022.9797095},
doi = {10.1109/MECO55406.2022.9797095},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/meco/RussoPMPLAC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mobiwis/CanzonieriMPRP22,
author = {Giuliano Canzonieri and
Salvatore Monteleone and
Maurizio Palesi and
Enrico Russo and
Davide Patti},
editor = {Irfan Awan and
Muhammad Younas and
Aneta Poniszewska{-}Maranda},
title = {Analyzing the Impact of {DNN} Hardware Accelerators-Oriented Compression
Techniques on General-Purpose Low-End Boards},
booktitle = {Mobile Web and Intelligent Information Systems - 18th International
Conference, MobiWIS 2022, Rome, Italy, August 22-24, 2022, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {13475},
pages = {143--155},
publisher = {Springer},
year = {2022},
url = {https://doi.org/10.1007/978-3-031-14391-5\_11},
doi = {10.1007/978-3-031-14391-5\_11},
timestamp = {Thu, 25 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mobiwis/CanzonieriMPRP22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2210-14657,
author = {Abhijit Das and
Enrico Russo and
Maurizio Palesi},
title = {Multi-Objective Hardware-Mapping Co-Optimisation for Multi-Tenant
{DNN} Accelerators},
journal = {CoRR},
volume = {abs/2210.14657},
year = {2022},
url = {https://doi.org/10.48550/arXiv.2210.14657},
doi = {10.48550/ARXIV.2210.14657},
eprinttype = {arXiv},
eprint = {2210.14657},
timestamp = {Wed, 02 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2210-14657.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/DahirKPMY21,
author = {Nizar Dahir and
Ammar Karkar and
Maurizio Palesi and
Terrence S. T. Mak and
Alex Yakovlev},
title = {Power density aware application mapping in mesh-based network-on-chip
architecture: An evolutionary multi-objective approach},
journal = {Integr.},
volume = {81},
pages = {342--353},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.08.008},
doi = {10.1016/J.VLSI.2021.08.008},
timestamp = {Wed, 03 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/DahirKPMY21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/DasKJP21,
author = {Abhijit Das and
Abhishek Kumar and
John Jose and
Maurizio Palesi},
title = {Opportunistic Caching in NoC: Exploring Ways to Reduce Miss Penalty},
journal = {{IEEE} Trans. Computers},
volume = {70},
number = {6},
pages = {892--905},
year = {2021},
url = {https://doi.org/10.1109/TC.2021.3069968},
doi = {10.1109/TC.2021.3069968},
timestamp = {Tue, 15 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/DasKJP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/XiaoWPSWM21,
author = {Siyuan Xiao and
Xiaohang Wang and
Maurizio Palesi and
Amit Kumar Singh and
Liang Wang and
Terrence S. T. Mak},
title = {On Performance Optimization and Quality Control for Approximate-Communication-Enabled
Networks-on-Chip},
journal = {{IEEE} Trans. Computers},
volume = {70},
number = {11},
pages = {1817--1830},
year = {2021},
url = {https://doi.org/10.1109/TC.2020.3027182},
doi = {10.1109/TC.2020.3027182},
timestamp = {Mon, 24 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/XiaoWPSWM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/DebJP21,
author = {Dipika Deb and
John Jose and
Maurizio Palesi},
title = {{COPE:} Reducing Cache Pollution and Network Contention by Inter-tile
Coordinated Prefetching in NoC-based MPSoCs},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {26},
number = {3},
pages = {17:1--17:31},
year = {2021},
url = {https://doi.org/10.1145/3428149},
doi = {10.1145/3428149},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/DebJP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nanocom/ZhiXHGWP0H21,
author = {Haocong Zhi and
Xianuo Xu and
Weijian Han and
Zhilin Gao and
Xiaohang Wang and
Maurizio Palesi and
Amit Kumar Singh and
Letian Huang},
editor = {Laura Galluccio and
Urbashi Mitra and
Maurizio Magarini and
Sergi Abada and
Michael Taynnan Barros and
Bhuvana Krishnaswamy},
title = {A Methodology for Simulating Multi-chiplet Systems Using Open-source
Simulators},
booktitle = {{NANOCOM} '21: The Eighth Annual {ACM} International Conference on
Nanoscale Computing and Communication, Virtual Event, Italy, September
7 - 9, 2021},
pages = {18:1--18:6},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3477206.3477459},
doi = {10.1145/3477206.3477459},
timestamp = {Mon, 24 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/nanocom/ZhiXHGWP0H21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/percom/RussoPMPAC21,
author = {Enrico Russo and
Maurizio Palesi and
Salvatore Monteleone and
Davide Patti and
Giuseppe Ascia and
Vincenzo Catania},
title = {{LAMBDA:} An Open Framework for Deep Neural Network Accelerators Simulation},
booktitle = {19th {IEEE} International Conference on Pervasive Computing and Communications
Workshops and other Affiliated Events, PerCom Workshops 2021, Kassel,
Germany, March 22-26, 2021},
pages = {161--166},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/PerComWorkshops51409.2021.9431078},
doi = {10.1109/PERCOMWORKSHOPS51409.2021.9431078},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/percom/RussoPMPAC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/cf/2021,
editor = {Maurizio Palesi and
Antonino Tumeo and
Georgios I. Goumas and
Carmen G. Almud{\'{e}}ver},
title = {{CF} '21: Computing Frontiers Conference, Virtual Event, Italy, May
11-13, 2021},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3457388},
doi = {10.1145/3457388},
isbn = {978-1-4503-8404-9},
timestamp = {Wed, 05 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cf/2021.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/CataniaMPP20,
author = {Vincenzo Catania and
Salvatore Monteleone and
Maurizio Palesi and
Davide Patti},
title = {Impact of Users' Beliefs in Text-Based Linguistic Interaction},
journal = {{IEEE} Access},
volume = {8},
pages = {46861--46867},
year = {2020},
url = {https://doi.org/10.1109/ACCESS.2020.2978977},
doi = {10.1109/ACCESS.2020.2978977},
timestamp = {Wed, 15 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/access/CataniaMPP20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cee/ShenYP20,
author = {Fangyang Shen and
Mei Yang and
Maurizio Palesi},
title = {Introduction to the special section on intelligent computing systems
and their applications},
journal = {Comput. Electr. Eng.},
volume = {85},
pages = {106816},
year = {2020},
url = {https://doi.org/10.1016/j.compeleceng.2020.106816},
doi = {10.1016/J.COMPELECENG.2020.106816},
timestamp = {Wed, 11 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/cee/ShenYP20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/esticas/ChenEPK20,
author = {Kun{-}Chih Chen and
Masoumeh Ebrahimi and
Maurizio Palesi and
Tim Kogel},
title = {Guest Editorial: Communication-Aware Designs and Methodologies for
Reliable and Adaptable On-Chip {AI} SubSystems and Accelerators},
journal = {{IEEE} J. Emerg. Sel. Topics Circuits Syst.},
volume = {10},
number = {3},
pages = {265--267},
year = {2020},
url = {https://doi.org/10.1109/JETCAS.2020.3023568},
doi = {10.1109/JETCAS.2020.3023568},
timestamp = {Thu, 17 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/esticas/ChenEPK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/esticas/NabavinejadBCPK20,
author = {Seyed Morteza Nabavinejad and
Mohammad Baharloo and
Kun{-}Chih Chen and
Maurizio Palesi and
Tim Kogel and
Masoumeh Ebrahimi},
title = {An Overview of Efficient Interconnection Networks for Deep Neural
Network Accelerators},
journal = {{IEEE} J. Emerg. Sel. Topics Circuits Syst.},
volume = {10},
number = {3},
pages = {268--282},
year = {2020},
url = {https://doi.org/10.1109/JETCAS.2020.3022920},
doi = {10.1109/JETCAS.2020.3022920},
timestamp = {Thu, 27 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/esticas/NabavinejadBCPK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jetc/AsciaCMPPJS20,
author = {Giuseppe Ascia and
Vincenzo Catania and
Salvatore Monteleone and
Maurizio Palesi and
Davide Patti and
John Jose and
Valerio Mario Salerno},
title = {Exploiting Data Resilience in Wireless Network-on-chip Architectures},
journal = {{ACM} J. Emerg. Technol. Comput. Syst.},
volume = {16},
number = {2},
pages = {21:1--21:27},
year = {2020},
url = {https://doi.org/10.1145/3379448},
doi = {10.1145/3379448},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jetc/AsciaCMPPJS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/PalesiCR20,
author = {Maurizio Palesi and
Kun{-}Chih Jimmy Chen and
Midia Reshadi},
title = {Special issue on energy-efficient many-core embedded systems and architectures
{(SI:} NoCArc18)},
journal = {J. Syst. Archit.},
volume = {109},
pages = {101822},
year = {2020},
url = {https://doi.org/10.1016/j.sysarc.2020.101822},
doi = {10.1016/J.SYSARC.2020.101822},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jsa/PalesiCR20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/topc/MonemiKPS20,
author = {Alireza Monemi and
Farshad Khunjush and
Maurizio Palesi and
Hamid Sarbazi{-}Azad},
title = {An Enhanced Dynamic Weighted Incremental Technique for QoS Support
in NoC},
journal = {{ACM} Trans. Parallel Comput.},
volume = {7},
number = {2},
pages = {9:1--9:31},
year = {2020},
url = {https://doi.org/10.1145/3391442},
doi = {10.1145/3391442},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/topc/MonemiKPS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aina/MnejjaAAMPP20,
author = {Sirine Mnejja and
Yassine Aydi and
Mohamed Abid and
Salvatore Monteleone and
Maurizio Palesi and
Davide Patti},
editor = {Leonard Barolli and
Flora Amato and
Francesco Moscato and
Tomoya Enokido and
Makoto Takizawa},
title = {Implementing On-Chip Wireless Communication in Multi-stage Interconnection
NoCs},
booktitle = {Advanced Information Networking and Applications - Proceedings of
the 34th International Conference on Advanced Information Networking
and Applications, AINA-2020, Caserta, Italy, 15-17 April},
series = {Advances in Intelligent Systems and Computing},
volume = {1151},
pages = {533--546},
publisher = {Springer},
year = {2020},
url = {https://doi.org/10.1007/978-3-030-44041-1\_48},
doi = {10.1007/978-3-030-44041-1\_48},
timestamp = {Thu, 04 Apr 2024 17:08:28 +0200},
biburl = {https://dblp.org/rec/conf/aina/MnejjaAAMPP20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/coins/MineoPPC20,
author = {Andrea Mineo and
Maurizio Palesi and
Davide Patti and
Vincenzo Catania},
title = {Cloud-Based Energy Efficient Scheme for Sigfox Monarch as Asset Tracking
Service},
booktitle = {2020 International Conference on Omni-layer Intelligent Systems, {COINS}
2020, Barcelona, Spain, August 31 - September 2, 2020},
pages = {1--6},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/COINS49042.2020.9191398},
doi = {10.1109/COINS49042.2020.9191398},
timestamp = {Tue, 22 Sep 2020 09:56:44 +0200},
biburl = {https://dblp.org/rec/conf/coins/MineoPPC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/LorandelLBMP20,
author = {Jordane Lorandel and
Habiba Lahdhiri and
Emmanuelle Bourdel and
Salvatore Monteleone and
Maurizio Palesi},
title = {Efficient Compression Technique for NoC-based Deep Neural Network
Accelerators},
booktitle = {23rd Euromicro Conference on Digital System Design, {DSD} 2020, Kranj,
Slovenia, August 26-28, 2020},
pages = {174--179},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/DSD51259.2020.00037},
doi = {10.1109/DSD51259.2020.00037},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dsd/LorandelLBMP20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/LahdhiriPMPALBC20,
author = {Habiba Lahdhiri and
Maurizio Palesi and
Salvatore Monteleone and
Davide Patti and
Giuseppe Ascia and
Jordane Lorandel and
Emmanuelle Bourdel and
Vincenzo Catania},
title = {DNNZip: Selective Layers Compression Technique in Deep Neural Network
Accelerators},
booktitle = {23rd Euromicro Conference on Digital System Design, {DSD} 2020, Kranj,
Slovenia, August 26-28, 2020},
pages = {526--533},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/DSD51259.2020.00088},
doi = {10.1109/DSD51259.2020.00088},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dsd/LahdhiriPMPALBC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/AsciaCJMPP20,
author = {Giuseppe Ascia and
Vincenzo Catania and
John Jose and
Salvatore Monteleone and
Maurizio Palesi and
Davide Patti},
title = {Improving Inference Latency and Energy of Network-on-Chip based Convolutional
Neural Networks through Weights Compression},
booktitle = {2020 {IEEE} International Parallel and Distributed Processing Symposium
Workshops, {IPDPSW} 2020, New Orleans, LA, USA, May 18-22, 2020},
pages = {54--63},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/IPDPSW50202.2020.00017},
doi = {10.1109/IPDPSW50202.2020.00017},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ipps/AsciaCJMPP20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/0002KJP20,
author = {Abhijit Das and
Abhishek Kumar and
John Jose and
Maurizio Palesi},
title = {Exploiting On-Chip Routers to Store Dirty Cache Blocks in Tiled Chip
Multi-processors},
booktitle = {2020 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2020,
Limassol, Cyprus, July 6-8, 2020},
pages = {147--152},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISVLSI49217.2020.00036},
doi = {10.1109/ISVLSI49217.2020.00036},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isvlsi/0002KJP20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nocs/AsciaCMMPP20,
author = {Giuseppe Ascia and
Vincenzo Catania and
Andrea Mineo and
Salvatore Monteleone and
Maurizio Palesi and
Davide Patti},
title = {Improving Inference Latency and Energy of DNNs through Wireless Enabled
Multi-Chip-Module-based Architectures and Model Parameters Compression},
booktitle = {14th {IEEE/ACM} International Symposium on Networks-on-Chip, {NOCS}
2020, Hamburg, Germany, September 24-25, 2020},
pages = {1--6},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/NOCS50636.2020.9241714},
doi = {10.1109/NOCS50636.2020.9241714},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/nocs/AsciaCMMPP20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/cf/2020,
editor = {Maurizio Palesi and
Gianluca Palermo and
Catherine Graves and
Eishi Arima},
title = {Proceedings of the 17th {ACM} International Conference on Computing
Frontiers, {CF} 2020, Catania, Sicily, Italy, May 11-13, 2020},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3387902},
doi = {10.1145/3387902},
isbn = {978-1-4503-7956-4},
timestamp = {Tue, 02 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cf/2020.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/DebJP19,
author = {Dipika Deb and
John Jose and
Maurizio Palesi},
title = {{ECAP:} energy-efficient caching for prefetch blocks in tiled chip
multiprocessors},
journal = {{IET} Comput. Digit. Tech.},
volume = {13},
number = {6},
pages = {417--428},
year = {2019},
url = {https://doi.org/10.1049/iet-cdt.2019.0035},
doi = {10.1049/IET-CDT.2019.0035},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/iet-cdt/DebJP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/XiaoWPSM19,
author = {Siyuan Xiao and
Xiaohang Wang and
Maurizio Palesi and
Amit Kumar Singh and
Terrence S. T. Mak},
editor = {J{\"{u}}rgen Teich and
Franco Fummi},
title = {{ACDC:} An Accuracy- and Congestion-aware Dynamic Traffic Control
Method for Networks-on-Chip},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2019, Florence, Italy, March 25-29, 2019},
pages = {630--633},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/DATE.2019.8715189},
doi = {10.23919/DATE.2019.8715189},
timestamp = {Mon, 24 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/XiaoWPSM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iotsms/AsciaCMPPJ19,
author = {Giuseppe Ascia and
Vincenzo Catania and
Salvatore Monteleone and
Maurizio Palesi and
Davide Patti and
John Jose},
editor = {Mohammad A. Alsmirat and
Yaser Jararweh},
title = {Networks-on-Chip based Deep Neural Networks Accelerators for IoT Edge
Devices},
booktitle = {Sixth International Conference on Internet of Things: Systems, Management
and Security, {IOTSMS} 2019, Granada, Spain, October 22-25, 2019},
pages = {227--234},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/IOTSMS48152.2019.8939236},
doi = {10.1109/IOTSMS48152.2019.8939236},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iotsms/AsciaCMPPJ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/TangP19,
author = {Minghua Tang and
Maurizio Palesi},
editor = {Kun{-}Chih Jimmy Chen and
Sergi Abadal and
Salvatore Monteleone},
title = {Study on logic-based routing for 3D NOCs},
booktitle = {Proceedings of the 12th International Workshop on Network on Chip
Architectures, NoCArc@MICRO 2019, Columbus, OH, USA, October 13, 2019},
pages = {12:1--12:6},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3356045.3360717},
doi = {10.1145/3356045.3360717},
timestamp = {Sun, 10 Nov 2019 16:12:18 +0100},
biburl = {https://dblp.org/rec/conf/micro/TangP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nocs/AsciaCMPPJ19,
author = {Giuseppe Ascia and
Vincenzo Catania and
Salvatore Monteleone and
Maurizio Palesi and
Davide Patti and
John Jose},
editor = {Paul Bogdan and
Cristina Silvano},
title = {Analyzing networks-on-chip based deep neural networks},
booktitle = {Proceedings of the 13th {IEEE/ACM} International Symposium on Networks-on-Chip,
{NOCS} 2019, New York, NY, USA, October 17-18, 2019},
pages = {23:1--23:2},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3313231.3352375},
doi = {10.1145/3313231.3352375},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/nocs/AsciaCMPPJ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/DebJP19,
author = {Dipika Deb and
John Jose and
Maurizio Palesi},
title = {Performance Enhancement of Caches in TCMPs Using Near Vicinity Prefetcher},
booktitle = {32nd International Conference on {VLSI} Design and 18th International
Conference on Embedded Systems, {VLSID} 2019, Delhi, India, January
5-9, 2019},
pages = {13--18},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSID.2019.00021},
doi = {10.1109/VLSID.2019.00021},
timestamp = {Mon, 14 Nov 2022 15:28:06 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/DebJP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/apin/KhanAGIPA18,
author = {Sarzamin Khan and
Sheraz Anjum and
Usman Ali Gulzari and
Farruh Ishmanov and
Maurizio Palesi and
Muhammad Khalil Afzal},
title = {An optimized hybrid algorithm in term of energy and performance for
mapping real time workloads on 2d based on-chip networks},
journal = {Appl. Intell.},
volume = {48},
number = {12},
pages = {4792--4804},
year = {2018},
url = {https://doi.org/10.1007/s10489-018-1246-7},
doi = {10.1007/S10489-018-1246-7},
timestamp = {Fri, 30 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/apin/KhanAGIPA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jetc/CataniaMMPP18,
author = {Vincenzo Catania and
Andrea Mineo and
Salvatore Monteleone and
Maurizio Palesi and
Davide Patti},
title = {Improving Energy Efficiency in Wireless Network-on-Chip Architectures},
journal = {{ACM} J. Emerg. Technol. Comput. Syst.},
volume = {14},
number = {1},
pages = {9:1--9:24},
year = {2018},
url = {https://doi.org/10.1145/3138807},
doi = {10.1145/3138807},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jetc/CataniaMMPP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/TangLP18,
author = {Minghua Tang and
Jing Lin and
Maurizio Palesi},
title = {The Suboptimal Routing Algorithm for 2D Mesh Network},
journal = {{IEEE} Trans. Computers},
volume = {67},
number = {5},
pages = {704--716},
year = {2018},
url = {https://doi.org/10.1109/TC.2017.2775643},
doi = {10.1109/TC.2017.2775643},
timestamp = {Tue, 17 Apr 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/TangLP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dcis/AsciaCMPPJ18,
author = {Giuseppe Ascia and
Vincenzo Catania and
Salvatore Monteleone and
Maurizio Palesi and
Davide Patti and
John Jose},
title = {Approximate Wireless Networks-on-Chip},
booktitle = {Conference on Design of Circuits and Integrated Systems, {DCIS} 2018,
Lyon, France, November 14-16, 2018},
pages = {1--6},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/DCIS.2018.8681491},
doi = {10.1109/DCIS.2018.8681491},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dcis/AsciaCMPPJ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/meco/AsciaCMPPJ18,
author = {Giuseppe Ascia and
Vincenzo Catania and
Salvatore Monteleone and
Maurizio Palesi and
Davide Patti and
John Jose},
title = {Improving energy consumption of NoC based architectures through approximate
communication},
booktitle = {7th Mediterranean Conference on Embedded Computing, {MECO} 2018, Budva,
Montenegro, June 10-14, 2018},
pages = {1--4},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/MECO.2018.8406045},
doi = {10.1109/MECO.2018.8406045},
timestamp = {Mon, 09 Aug 2021 14:54:01 +0200},
biburl = {https://dblp.org/rec/conf/meco/AsciaCMPPJ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nocs/0002BJJP18,
author = {Abhijit Das and
Sarath Babu and
John Jose and
Sangeetha Jose and
Maurizio Palesi},
editor = {Zhonghai Lu and
Sriram R. Vangal and
Jiang Xu and
Paul Bogdan},
title = {Critical Packet Prioritisation by Slack-Aware Re-Routing in On-Chip
Networks},
booktitle = {Twelfth {IEEE/ACM} International Symposium on Networks-on-Chip, {NOCS}
2018, Torino, Italy, October 4-5, 2018},
pages = {12:1--12:8},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/NOCS.2018.8512164},
doi = {10.1109/NOCS.2018.8512164},
timestamp = {Fri, 30 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/nocs/0002BJJP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/peccs/BiondiCMPP18,
author = {Salvatore Michele Biondi and
Vincenzo Catania and
Salvatore Monteleone and
Maurizio Palesi and
Davide Patti},
editor = {Luis Gomes and
Andreas Ahrens and
C{\'{e}}sar Benavente{-}Peces and
Mohammad S. Obaidat},
title = {smARTworks: {A} Multi-sided Context-aware Platform for the Smart Museum},
booktitle = {Proceedings of the 8th International Joint Conference on Pervasive
and Embedded Computing and Communication Systems, {PECCS} 2018, Porto,
Portugal, July 29-30, 2018},
pages = {241--247},
publisher = {SciTePress},
year = {2018},
url = {https://doi.org/10.5220/0006907302410247},
doi = {10.5220/0006907302410247},
timestamp = {Wed, 29 Aug 2018 15:27:26 +0200},
biburl = {https://dblp.org/rec/conf/peccs/BiondiCMPP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/supercomputer/CataniaMPP18,
author = {Vincenzo Catania and
Salvatore Monteleone and
Maurizio Palesi and
Davide Patti},
editor = {Rio Yokota and
Mich{\`{e}}le Weiland and
David E. Keyes and
Carsten Trinitis},
title = {Packetization of Shared-Memory Traces for Message Passing Oriented
NoC Simulation},
booktitle = {High Performance Computing - 33rd International Conference, {ISC}
High Performance 2018, Frankfurt, Germany, June 24-28, 2018, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {10876},
pages = {311--325},
publisher = {Springer},
year = {2018},
url = {https://doi.org/10.1007/978-3-319-92040-5\_16},
doi = {10.1007/978-3-319-92040-5\_16},
timestamp = {Tue, 14 May 2019 10:00:40 +0200},
biburl = {https://dblp.org/rec/conf/supercomputer/CataniaMPP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SleebaJPJM18,
author = {Simi Zerine Sleeba and
John Jose and
Maurizio Palesi and
Rekha K. James and
Maniyelil Govindankutty Mini},
title = {Traffic Aware Deflection Rerouting Mechanism for Mesh Network on Chip},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {25--30},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8645011},
doi = {10.1109/VLSI-SOC.2018.8645011},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SleebaJPJM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/MonemiTPM17,
author = {Alireza Monemi and
Jia Wei Tang and
Maurizio Palesi and
Muhammad N. Marsono},
title = {ProNoC: {A} low latency network-on-chip based many-core system-on-chip
prototyping platform},
journal = {Microprocess. Microsystems},
volume = {54},
pages = {60--74},
year = {2017},
url = {https://doi.org/10.1016/j.micpro.2017.08.007},
doi = {10.1016/J.MICPRO.2017.08.007},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mam/MonemiTPM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mj/MonemiOPM17,
author = {Alireza Monemi and
Chia Yee Ooi and
Maurizio Palesi and
Muhammad N. Marsono},
title = {Ping-lock round robin arbiter},
journal = {Microelectron. J.},
volume = {63},
pages = {81--93},
year = {2017},
url = {https://doi.org/10.1016/j.mejo.2017.03.004},
doi = {10.1016/J.MEJO.2017.03.004},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mj/MonemiOPM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/TangLP17,
author = {Minghua Tang and
Xiaola Lin and
Maurizio Palesi},
title = {The Repetitive Turn Model for Adaptive Routing},
journal = {{IEEE} Trans. Computers},
volume = {66},
number = {1},
pages = {138--146},
year = {2017},
url = {https://doi.org/10.1109/TC.2016.2564961},
doi = {10.1109/TC.2016.2564961},
timestamp = {Wed, 14 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tc/TangLP17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/MoreacLBRBP17,
author = {Erwan Moreac and
Johann Laurent and
Pierre Bomel and
Andr{\'{e}} Rossi and
Emmanuel Boutillon and
Maurizio Palesi},
title = {Energy aware Networks-on-Chip cortex inspired communication},
booktitle = {27th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2017, Thessaloniki, Greece, September 25-27,
2017},
pages = {1--8},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/PATMOS.2017.8106952},
doi = {10.1109/PATMOS.2017.8106952},
timestamp = {Wed, 16 Oct 2019 14:14:57 +0200},
biburl = {https://dblp.org/rec/conf/patmos/MoreacLBRBP17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcss/PalesiCDB16,
author = {Maurizio Palesi and
Mario Collotta and
Masoud Daneshtalab and
Pradip Bose},
title = {Special issue on energy efficient methods and systems in the emerging
cloud era},
journal = {J. Comput. Syst. Sci.},
volume = {82},
number = {2},
pages = {173},
year = {2016},
url = {https://doi.org/10.1016/j.jcss.2015.11.006},
doi = {10.1016/J.JCSS.2015.11.006},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jcss/PalesiCDB16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/BakhouyaDPG16,
author = {Mohamed Bakhouya and
Masoud Daneshtalab and
Maurizio Palesi and
Hassan Ghasemzadeh},
title = {Many-core System-on-Chip: architectures and applications},
journal = {Microprocess. Microsystems},
volume = {43},
pages = {1--3},
year = {2016},
url = {https://doi.org/10.1016/j.micpro.2016.05.002},
doi = {10.1016/J.MICPRO.2016.05.002},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mam/BakhouyaDPG16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/MineoPAC16,
author = {Andrea Mineo and
Maurizio Palesi and
Giuseppe Ascia and
Vincenzo Catania},
title = {Exploiting antenna directivity in wireless NoC architectures},
journal = {Microprocess. Microsystems},
volume = {43},
pages = {59--66},
year = {2016},
url = {https://doi.org/10.1016/j.micpro.2016.01.019},
doi = {10.1016/J.MICPRO.2016.01.019},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mam/MineoPAC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/ShenPY16,
author = {Fangyang Shen and
Maurizio Palesi and
Mei Yang},
title = {Introduction to the special section on "Sustainable processor
architectures and applications"},
journal = {Microprocess. Microsystems},
volume = {46},
pages = {105--106},
year = {2016},
url = {https://doi.org/10.1016/j.micpro.2016.07.018},
doi = {10.1016/J.MICPRO.2016.07.018},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mam/ShenPY16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MineoPAPC16,
author = {Andrea Mineo and
Maurizio Palesi and
Giuseppe Ascia and
Partha Pratim Pande and
Vincenzo Catania},
title = {On-Chip Communication Energy Reduction Through Reliability Aware Adaptive
Voltage Swing Scaling},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {35},
number = {11},
pages = {1769--1782},
year = {2016},
url = {https://doi.org/10.1109/TCAD.2016.2524556},
doi = {10.1109/TCAD.2016.2524556},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MineoPAPC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tomacs/CataniaMMPP16,
author = {Vincenzo Catania and
Andrea Mineo and
Salvatore Monteleone and
Maurizio Palesi and
Davide Patti},
title = {Cycle-Accurate Network on Chip Simulation with Noxim},
journal = {{ACM} Trans. Model. Comput. Simul.},
volume = {27},
number = {1},
pages = {4},
year = {2016},
url = {https://doi.org/10.1145/2953878},
doi = {10.1145/2953878},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tomacs/CataniaMMPP16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tpds/TangLP16,
author = {Minghua Tang and
Xiaola Lin and
Maurizio Palesi},
title = {Local Congestion Avoidance in Network-on-Chip},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {27},
number = {7},
pages = {2062--2073},
year = {2016},
url = {https://doi.org/10.1109/TPDS.2015.2474375},
doi = {10.1109/TPDS.2015.2474375},
timestamp = {Fri, 02 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tpds/TangLP16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MineoPAC16,
author = {Andrea Mineo and
Maurizio Palesi and
Giuseppe Ascia and
Vincenzo Catania},
title = {Runtime Tunable Transmitting Power Technique in mm-Wave WiNoC Architectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {24},
number = {4},
pages = {1535--1545},
year = {2016},
url = {https://doi.org/10.1109/TVLSI.2015.2449275},
doi = {10.1109/TVLSI.2015.2449275},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MineoPAC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ccnc/CataniaMMPP16,
author = {Vincenzo Catania and
Andrea Mineo and
Salvatore Monteleone and
Maurizio Palesi and
Davide Patti},
title = {Improving the energy efficiency of wireless Network on Chip architectures
through online selective buffers and receivers shutdown},
booktitle = {13th {IEEE} Annual Consumer Communications {\&} Networking Conference,
{CCNC} 2016, Las Vegas, NV, USA, January 9-12, 2016},
pages = {668--673},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/CCNC.2016.7444860},
doi = {10.1109/CCNC.2016.7444860},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/ccnc/CataniaMMPP16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/CataniaMMPP16,
author = {Vincenzo Catania and
Andrea Mineo and
Salvatore Monteleone and
Maurizio Palesi and
Davide Patti},
editor = {Luca Fanucci and
J{\"{u}}rgen Teich},
title = {Energy efficient transceiver in wireless Network on Chip architectures},
booktitle = {2016 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2016, Dresden, Germany, March 14-18, 2016},
pages = {1321--1326},
publisher = {{IEEE}},
year = {2016},
url = {https://ieeexplore.ieee.org/document/7459514/},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/CataniaMMPP16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/MonemiOMP16,
author = {Alireza Monemi and
Chia Yee Ooi and
Muhammad Nadzir Marsono and
Maurizio Palesi},
title = {Improved Flow Control for Minimal Fully Adaptive Routing in 2D Mesh
NoC},
booktitle = {Proceedings of the 9th International Workshop on Network on Chip Architectures,
NoCArc@MICRO 2016, Taipei, Taiwan, October 15, 2016},
pages = {9--14},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2994133.2994134},
doi = {10.1145/2994133.2994134},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/micro/MonemiOMP16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/pdp/RezaeiDPZ16,
author = {Amin Rezaei and
Masoud Daneshtalab and
Maurizio Palesi and
Danella Zhao},
title = {Efficient Congestion-Aware Scheme for Wireless on-Chip Networks},
booktitle = {24th Euromicro International Conference on Parallel, Distributed,
and Network-Based Processing, {PDP} 2016, Heraklion, Crete, Greece,
February 17-19, 2016},
pages = {742--749},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/PDP.2016.88},
doi = {10.1109/PDP.2016.88},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/pdp/RezaeiDPZ16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cee/ShenLP15,
author = {Fangyang Shen and
Lingjia Liu and
Maurizio Palesi},
title = {Introduction to the special issue on "Emerging research in Internet
of Things"},
journal = {Comput. Electr. Eng.},
volume = {44},
pages = {104--106},
year = {2015},
url = {https://doi.org/10.1016/j.compeleceng.2015.05.016},
doi = {10.1016/J.COMPELECENG.2015.05.016},
timestamp = {Wed, 19 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/cee/ShenLP15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cee/DaneshtalabPM15,
author = {Masoud Daneshtalab and
Maurizio Palesi and
Terrence S. T. Mak},
title = {Introduction to the special issue on NoC-based many-core architectures},
journal = {Comput. Electr. Eng.},
volume = {45},
pages = {359--361},
year = {2015},
url = {https://doi.org/10.1016/j.compeleceng.2015.07.010},
doi = {10.1016/J.COMPELECENG.2015.07.010},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/cee/DaneshtalabPM15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcsci/PalesiPAPC15,
author = {Maurizio Palesi and
Davide Patti and
Giuseppe Ascia and
Daniela Panno and
Vincenzo Catania},
title = {Coupling Routing Algorithm and Data Encoding for Low Power Networks
on Chip},
journal = {J. Comput. Sci.},
volume = {11},
number = {3},
pages = {552--566},
year = {2015},
url = {https://doi.org/10.3844/jcssp.2015.552.566},
doi = {10.3844/JCSSP.2015.552.566},
timestamp = {Sat, 25 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jcsci/PalesiPAPC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TangLP15,
author = {Minghua Tang and
Xiaola Lin and
Maurizio Palesi},
title = {An Offline Method for Designing Adaptive Routing Based on Pressure
Model},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {34},
number = {2},
pages = {307--320},
year = {2015},
url = {https://doi.org/10.1109/TCAD.2014.2379649},
doi = {10.1109/TCAD.2014.2379649},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TangLP15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JafarzadehPEHA15,
author = {Nima Jafarzadeh and
Maurizio Palesi and
Saeedeh Eskandari and
Shaahin Hessabi and
Ali Afzali{-}Kusha},
title = {Low Energy yet Reliable Data Communication Scheme for Network-on-Chip},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {34},
number = {12},
pages = {1892--1904},
year = {2015},
url = {https://doi.org/10.1109/TCAD.2015.2440311},
doi = {10.1109/TCAD.2015.2440311},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JafarzadehPEHA15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tpds/TangLP15,
author = {Minghua Tang and
Xiaola Lin and
Maurizio Palesi},
title = {Routing Pressure: {A} Channel-Related and Traffic-Aware Metric of
Routing Algorithm},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {26},
number = {3},
pages = {891--901},
year = {2015},
url = {https://doi.org/10.1109/TPDS.2013.184},
doi = {10.1109/TPDS.2013.184},
timestamp = {Fri, 02 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tpds/TangLP15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asap/CataniaMMPP15,
author = {Vincenzo Catania and
Andrea Mineo and
Salvatore Monteleone and
Maurizio Palesi and
Davide Patti},
title = {Noxim: An open, extensible and cycle-accurate network on chip simulator},
booktitle = {26th {IEEE} International Conference on Application-specific Systems,
Architectures and Processors, {ASAP} 2015, Toronto, ON, Canada, July
27-29, 2015},
pages = {162--163},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/ASAP.2015.7245728},
doi = {10.1109/ASAP.2015.7245728},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asap/CataniaMMPP15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/MineoRPACM15,
author = {Andrea Mineo and
Mohd Shahrizal Rusli and
Maurizio Palesi and
Giuseppe Ascia and
Vincenzo Catania and
Muhammad N. Marsono},
editor = {Wolfgang Nebel and
David Atienza},
title = {A closed loop transmitting power self-calibration scheme for energy
efficient WiNoC architectures},
booktitle = {Proceedings of the 2015 Design, Automation {\&} Test in Europe
Conference {\&} Exhibition, {DATE} 2015, Grenoble, France, March
9-13, 2015},
pages = {513--518},
publisher = {{ACM}},
year = {2015},
url = {http://dl.acm.org/citation.cfm?id=2755869},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/MineoRPACM15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/estimedia/OhSSP15,
author = {Hyunok Oh and
Muhammad Shafique and
Todor P. Stefanov and
Maurizio Palesi},
title = {Message from the Chairs},
booktitle = {13th {IEEE} Symposium on Embedded Systems For Real-time Multimedia,
ESTIMedia 2015, Amsterdam, The Netherlands, October 8-9, 2015},
pages = {1},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ESTIMedia.2015.7351759},
doi = {10.1109/ESTIMEDIA.2015.7351759},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/estimedia/OhSSP15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/isca/2015mes,
editor = {Masoumeh Ebrahimi and
Diana Goehringer and
Masoud Daneshtalab and
Maurizio Palesi and
S{\"{o}}ren Sonntag and
Federico Angiolini},
title = {Proceedings of the 3rd International Workshop on Many-core Embedded
Systems (MES'2015) held on June 13, 2015 in conjunction with the 42nd
International Symposium on Computer Architecture (ISCA'2015), Portland,
OR, {USA}},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2768177},
doi = {10.1145/2768177},
isbn = {978-1-4503-3408-2},
timestamp = {Fri, 09 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isca/2015mes.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cee/DaneshtalabPM14,
author = {Masoud Daneshtalab and
Maurizio Palesi and
Terrence S. T. Mak},
title = {Introduction to the Special Issue on Network-on-Chip Architectures},
journal = {Comput. Electr. Eng.},
volume = {40},
number = {8},
pages = {257--259},
year = {2014},
url = {https://doi.org/10.1016/j.compeleceng.2014.11.005},
doi = {10.1016/J.COMPELECENG.2014.11.005},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/cee/DaneshtalabPM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/DaneshtalabPPH14,
author = {Masoud Daneshtalab and
Maurizio Palesi and
Juha Plosila and
Ahmed Hemani},
title = {Special issue on many-core embedded systems},
journal = {Microprocess. Microsystems},
volume = {38},
number = {6},
pages = {525},
year = {2014},
url = {https://doi.org/10.1016/j.micpro.2014.07.002},
doi = {10.1016/J.MICPRO.2014.07.002},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mam/DaneshtalabPPH14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tecs/WangYJ0DPM14,
author = {Xiaohang Wang and
Mei Yang and
Yingtao Jiang and
Peng Liu and
Masoud Daneshtalab and
Maurizio Palesi and
Terrence S. T. Mak},
title = {On self-tuning networks-on-chip for dynamic network-flow dominance
adaptation},
journal = {{ACM} Trans. Embed. Comput. Syst.},
volume = {13},
number = {2s},
pages = {73:1--73:21},
year = {2014},
url = {https://doi.org/10.1145/2544375.2544393},
doi = {10.1145/2544375.2544393},
timestamp = {Mon, 24 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tecs/WangYJ0DPM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tecs/DaneshtalabPP14,
author = {Masoud Daneshtalab and
Maurizio Palesi and
Juha Plosila},
title = {Editorial: Special issue on design challenges for many-core processors},
journal = {{ACM} Trans. Embed. Comput. Syst.},
volume = {13},
number = {3s},
pages = {100:1--100:2},
year = {2014},
url = {https://doi.org/10.1145/2567941},
doi = {10.1145/2567941},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tecs/DaneshtalabPP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tecs/PalesiS14,
author = {Maurizio Palesi and
Todor P. Stefanov},
title = {Editorial: Special Section on ESTIMedia'13},
journal = {{ACM} Trans. Embed. Comput. Syst.},
volume = {13},
number = {3s},
pages = {110:1},
year = {2014},
url = {https://doi.org/10.1145/2567942},
doi = {10.1145/2567942},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tecs/PalesiS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JafarzadehPKA14,
author = {Nima Jafarzadeh and
Maurizio Palesi and
Ahmad Khademzadeh and
Ali Afzali{-}Kusha},
title = {Data Encoding Techniques for Reducing Energy Consumption in Network-on-Chip},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {22},
number = {3},
pages = {675--685},
year = {2014},
url = {https://doi.org/10.1109/TVLSI.2013.2251020},
doi = {10.1109/TVLSI.2013.2251020},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JafarzadehPKA14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/csoc/PattiPC14,
author = {Davide Patti and
Maurizio Palesi and
Vincenzo Catania},
editor = {Radek Silhavy and
Roman Senkerik and
Zuzana Kom{\'{\i}}nkov{\'{a}} Oplatkov{\'{a}} and
Petr Silhavy and
Zdenka Prokopova},
title = {Merging Compilation and Microarchitectural Configuration Spaces for
Performance/Power Optimization in VLIW-Based Systems},
booktitle = {Modern Trends and Techniques in Computer Science - 3rd Computer Science
On-line Conference 2014 {(CSOC} 2014)},
series = {Advances in Intelligent Systems and Computing},
volume = {285},
pages = {203--212},
publisher = {Springer},
year = {2014},
url = {https://doi.org/10.1007/978-3-319-06740-7\_18},
doi = {10.1007/978-3-319-06740-7\_18},
timestamp = {Thu, 14 Oct 2021 10:34:33 +0200},
biburl = {https://dblp.org/rec/conf/csoc/PattiPC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/FattahPLPT14,
author = {Mohammad Fattah and
Maurizio Palesi and
Pasi Liljeberg and
Juha Plosila and
Hannu Tenhunen},
title = {SHiFA: System-Level Hierarchy in Run-Time Fault-Aware Management of
Many-Core Systems},
booktitle = {The 51st Annual Design Automation Conference 2014, {DAC} '14, San
Francisco, CA, USA, June 1-5, 2014},
pages = {101:1--101:6},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2593069.2593214},
doi = {10.1145/2593069.2593214},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/FattahPLPT14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/MineoPAC14,
author = {Andrea Mineo and
Maurizio Palesi and
Giuseppe Ascia and
Vincenzo Catania},
editor = {Gerhard P. Fettweis and
Wolfgang Nebel},
title = {An adaptive transmitting power technique for energy efficient mm-wave
wireless NoCs},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2014, Dresden, Germany, March 24-28, 2014},
pages = {1--6},
publisher = {European Design and Automation Association},
year = {2014},
url = {https://doi.org/10.7873/DATE.2014.284},
doi = {10.7873/DATE.2014.284},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/MineoPAC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/WangZMYJDP14,
author = {Xiaohang Wang and
Baoxin Zhao and
Terrence S. T. Mak and
Mei Yang and
Yingtao Jiang and
Masoud Daneshtalab and
Maurizio Palesi},
editor = {Gerhard P. Fettweis and
Wolfgang Nebel},
title = {Adaptive power allocation for many-core systems inspired from multiagent
auction model},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2014, Dresden, Germany, March 24-28, 2014},
pages = {1--4},
publisher = {European Design and Automation Association},
year = {2014},
url = {https://doi.org/10.7873/DATE.2014.346},
doi = {10.7873/DATE.2014.346},
timestamp = {Mon, 24 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/WangZMYJDP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/RusliMPACM14,
author = {Mohd Shahrizal Rusli and
Andrea Mineo and
Maurizio Palesi and
Giuseppe Ascia and
Vincenzo Catania and
Muhammad N. Marsono},
editor = {Masoud Daneshtalab and
Masoumeh Ebrahimi and
Maurizio Palesi and
Federico Angiolini and
Juha Plosila},
title = {A Closed Loop Control based Power Manager for WiNoC Architectures},
booktitle = {Proceedings of the 2nd International Workshop on Many-core Embedded
Systems, MES'2014, in conjunction with the 41st International Symposium
on Computer Architecture, ISCA'2014, Minneapolis, MN, USA, June 15,
2014},
pages = {60--63},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2613908.2613914},
doi = {10.1145/2613908.2613914},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isca/RusliMPACM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/isca/2014mes,
editor = {Masoud Daneshtalab and
Masoumeh Ebrahimi and
Maurizio Palesi and
Federico Angiolini and
Juha Plosila},
title = {Proceedings of the 2nd International Workshop on Many-core Embedded
Systems, MES'2014, in conjunction with the 41st International Symposium
on Computer Architecture, ISCA'2014, Minneapolis, MN, USA, June 15,
2014},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2613908},
doi = {10.1145/2613908},
isbn = {978-1-4503-2822-7},
timestamp = {Tue, 23 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isca/2014mes.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcst/WangLYPJH13,
author = {Xiaohang Wang and
Peng Liu and
Mei Yang and
Maurizio Palesi and
Yingtao Jiang and
Michael C. Huang},
title = {Energy Efficient Run-Time Incremental Mapping for 3-D Networks-on-Chip},
journal = {J. Comput. Sci. Technol.},
volume = {28},
number = {1},
pages = {54--71},
year = {2013},
url = {https://doi.org/10.1007/s11390-013-1312-x},
doi = {10.1007/S11390-013-1312-X},
timestamp = {Mon, 24 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jcst/WangLYPJH13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/WangYJP0MB13,
author = {Xiaohang Wang and
Mei Yang and
Yingtao Jiang and
Maurizio Palesi and
Peng Liu and
Terrence S. T. Mak and
Nader Bagherzadeh},
title = {Efficient multicast schemes for 3-D Networks-on-Chip},
journal = {J. Syst. Archit.},
volume = {59},
number = {9},
pages = {693--708},
year = {2013},
url = {https://doi.org/10.1016/j.sysarc.2013.06.002},
doi = {10.1016/J.SYSARC.2013.06.002},
timestamp = {Mon, 24 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jsa/WangYJP0MB13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/pc/ShenYP13,
author = {Fangyang Shen and
Mei Yang and
Maurizio Palesi},
title = {Guest Editors' Introduction to the Special Issue on "Novel On-Chip
Parallel Architectures and Software Support"},
journal = {Parallel Comput.},
volume = {39},
number = {9},
pages = {355--356},
year = {2013},
url = {https://doi.org/10.1016/j.parco.2013.08.001},
doi = {10.1016/J.PARCO.2013.08.001},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/pc/ShenYP13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tecs/ChenP13,
author = {Jian{-}Jia Chen and
Maurizio Palesi},
title = {Introduction to the special section on ESTIMedia'12},
journal = {{ACM} Trans. Embed. Comput. Syst.},
volume = {12},
number = {1s},
pages = {32:1--32:2},
year = {2013},
url = {https://doi.org/10.1145/2435227.2435228},
doi = {10.1145/2435227.2435228},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tecs/ChenP13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tecs/CardoP13,
author = {Jos{\'{e}} Flich Cardo and
Maurizio Palesi},
title = {Introduction to the special section on on-chip and off-chip network
architectures},
journal = {{ACM} Trans. Embed. Comput. Syst.},
volume = {12},
number = {4},
pages = {104:1--104:2},
year = {2013},
url = {https://doi.org/10.1145/2485984.2485992},
doi = {10.1145/2485984.2485992},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tecs/CardoP13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/AsciaPC13,
author = {Giuseppe Ascia and
Maurizio Palesi and
Vincenzo Catania},
title = {An Adaptive Output Selection Function Based on a Fuzzy Rule Base System
for Network on Chip},
booktitle = {2013 Euromicro Conference on Digital System Design, {DSD} 2013, Los
Alamitos, CA, USA, September 4-6, 2013},
pages = {505--512},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/DSD.2013.60},
doi = {10.1109/DSD.2013.60},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/AsciaPC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/MineoPAC13,
author = {Andrea Mineo and
Maurizio Palesi and
Giuseppe Ascia and
Vincenzo Catania},
title = {Runtime Online Links Voltage Scaling for Low Energy Networks on Chip},
booktitle = {2013 Euromicro Conference on Digital System Design, {DSD} 2013, Los
Alamitos, CA, USA, September 4-6, 2013},
pages = {941--944},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/DSD.2013.106},
doi = {10.1109/DSD.2013.106},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/MineoPAC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/estimedia/StefanovPCH13,
author = {Todor P. Stefanov and
Maurizio Palesi and
Jian{-}Jia Chen and
J{\"{o}}rg Henkel},
title = {Message from the chairs},
booktitle = {The 11th {IEEE} Symposium on Embedded Systems for Real-time Multimedia,
Montreal, QC, Canada, October 3-4, 2013},
pages = {1},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ESTIMedia.2013.6704493},
doi = {10.1109/ESTIMEDIA.2013.6704493},
timestamp = {Thu, 17 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/estimedia/StefanovPCH13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpcc/MineoMPAC13,
author = {Andrea Mineo and
Marina Masi and
Maurizio Palesi and
Giuseppe Ascia and
Vincenzo Catania},
title = {Low Energy Mapping Techniques under Reliability and Bandwidth Constraints},
booktitle = {10th {IEEE} International Conference on High Performance Computing
and Communications {\&} 2013 {IEEE} International Conference on
Embedded and Ubiquitous Computing, {HPCC/EUC} 2013, Zhangjiajie, China,
November 13-15, 2013},
pages = {2088--2095},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/HPCC.and.EUC.2013.300},
doi = {10.1109/HPCC.AND.EUC.2013.300},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/hpcc/MineoMPAC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nocs/WangMYJDP13,
author = {Xiaohang Wang and
Terrence S. T. Mak and
Mei Yang and
Yingtao Jiang and
Masoud Daneshtalab and
Maurizio Palesi},
title = {On self-tuning networks-on-chip for dynamic network-flow dominance
adaptation},
booktitle = {2013 Seventh {IEEE/ACM} International Symposium on Networks-on-Chip
(NoCS), Tempe, AZ, USA, April 21-24, 2013},
pages = {1--8},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/NoCS.2013.6558418},
doi = {10.1109/NOCS.2013.6558418},
timestamp = {Mon, 24 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/nocs/WangMYJDP13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/samos/MineoPAC13,
author = {Andrea Mineo and
Maurizio Palesi and
Giuseppe Ascia and
Vincenzo Catania},
title = {NoC links energy reduction through link voltage scaling},
booktitle = {2013 International Conference on Embedded Computer Systems: Architectures,
Modeling, and Simulation, {SAMOS} 2013, Agios Konstantinos, Samos
Island, Greece, July 15-18, 2013},
pages = {113--120},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/SAMOS.2013.6621113},
doi = {10.1109/SAMOS.2013.6621113},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/samos/MineoPAC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/isca/2013mes,
editor = {Masoud Daneshtalab and
Ahmed Hemani and
Maurizio Palesi},
title = {Proceedings of the 1st International Workshop on Many-core Embedded
Systems 2013, MES'2013, Held in conjunction with the 40th Annual {IEEE/ACM}
International Symposium on Computer Architecture, {ISCA} 2013, June
24, 2013},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2489068},
doi = {10.1145/2489068},
isbn = {978-1-4503-2063-4},
timestamp = {Fri, 09 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isca/2013mes.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/micro/2013nocarc,
editor = {Maurizio Palesi and
Terrence S. T. Mak and
Masoud Daneshtalab},
title = {Network on Chip Architectures, NoCArc '13, in conjunction with the
46th Annual {IEEE/ACM} International Symposium on Microarchitecture,
MICRO-46, Davis, CA, USA, December 7, 2013},
publisher = {{ACM}},
year = {2013},
url = {http://dl.acm.org/citation.cfm?id=2536522},
isbn = {978-1-4503-2370-3},
timestamp = {Thu, 22 Jan 2015 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/micro/2013nocarc.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cai/TorneroPD12,
author = {Rafael Tornero and
Maurizio Palesi and
Jos{\'{e}} Duato},
title = {A Topology-Independent Mapping Technique for Application-Specific
Networks-on-Chip},
journal = {Comput. Informatics},
volume = {31},
number = {5},
pages = {939--970},
year = {2012},
url = {http://www.cai.sk/ojs/index.php/cai/article/view/1312},
timestamp = {Mon, 14 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/cai/TorneroPD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cee/ShenYP12,
author = {Fangyang Shen and
Mei Yang and
Maurizio Palesi},
title = {Guest Editors' Introduction to the Special Issue on "Emerging
Computing Architectures and Systems"},
journal = {Comput. Electr. Eng.},
volume = {38},
number = {3},
pages = {722--723},
year = {2012},
url = {https://doi.org/10.1016/j.compeleceng.2012.03.016},
doi = {10.1016/J.COMPELECENG.2012.03.016},
timestamp = {Wed, 19 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/cee/ShenYP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jucs/PalesiTOCP12,
author = {Maurizio Palesi and
Rafael Tornero and
Juan Manuel Ordu{\~{n}}a and
Vincenzo Catania and
Daniela Panno},
title = {Designing Robust Routing Algorithms and Mapping Cores in Networks-on-Chip:
{A} Multi-objective Evolutionary-based Approach},
journal = {J. Univers. Comput. Sci.},
volume = {18},
number = {7},
pages = {937--969},
year = {2012},
url = {https://doi.org/10.3217/jucs-018-07-0937},
doi = {10.3217/JUCS-018-07-0937},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jucs/PalesiTOCP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/te/PattiSPFC12,
author = {Davide Patti and
Andrea Spadaccini and
Maurizio Palesi and
Fabrizio Fazzino and
Vincenzo Catania},
title = {Supporting Undergraduate Computer Architecture Students Using a Visual
{MIPS64} {CPU} Simulator},
journal = {{IEEE} Trans. Educ.},
volume = {55},
number = {3},
pages = {406--411},
year = {2012},
url = {https://doi.org/10.1109/TE.2011.2180530},
doi = {10.1109/TE.2011.2180530},
timestamp = {Thu, 16 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/te/PattiSPFC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tpds/Al-DujailyMXYP12,
author = {Ra'ed Al{-}Dujaily and
Terrence S. T. Mak and
Fei Xia and
Alex Yakovlev and
Maurizio Palesi},
title = {Embedded Transitive Closure Network for Runtime Deadlock Detection
in Networks-on-Chip},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {23},
number = {7},
pages = {1205--1215},
year = {2012},
url = {https://doi.org/10.1109/TPDS.2011.275},
doi = {10.1109/TPDS.2011.275},
timestamp = {Fri, 02 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tpds/Al-DujailyMXYP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nocs/EbrahimiDFPLPT12,
author = {Masoumeh Ebrahimi and
Masoud Daneshtalab and
Fahimeh Farahnakian and
Juha Plosila and
Pasi Liljeberg and
Maurizio Palesi and
Hannu Tenhunen},
title = {{HARAQ:} Congestion-Aware Learning Model for Highly Adaptive Routing
Algorithm in On-Chip Networks},
booktitle = {2012 Sixth {IEEE/ACM} International Symposium on Networks-on-Chip
(NoCS), Copenhagen, Denmark, 9-11 May, 2012},
pages = {19--26},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/NOCS.2012.10},
doi = {10.1109/NOCS.2012.10},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/nocs/EbrahimiDFPLPT12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/micro/2012nocarc,
editor = {Maurizio Palesi and
Terrence S. T. Mak},
title = {Fifth International Workshop on Network on Chip Architectures, NoCArc
'12, Vancouver, BC, Canada, December 1, 2012},
publisher = {{ACM}},
year = {2012},
url = {http://dl.acm.org/citation.cfm?id=2401716},
isbn = {978-1-4503-1540-1},
timestamp = {Thu, 02 Jan 2014 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/micro/2012nocarc.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/asc/AsciaCNPP11,
author = {Giuseppe Ascia and
Vincenzo Catania and
Alessandro G. Di Nuovo and
Maurizio Palesi and
Davide Patti},
title = {Performance evaluation of efficient multi-objective evolutionary algorithms
for design space exploration of embedded computer systems},
journal = {Appl. Soft Comput.},
volume = {11},
number = {1},
pages = {382--398},
year = {2011},
url = {https://doi.org/10.1016/j.asoc.2009.11.029},
doi = {10.1016/J.ASOC.2009.11.029},
timestamp = {Fri, 30 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/asc/AsciaCNPP11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/PalesiKM11,
author = {Maurizio Palesi and
Shashi Kumar and
Radu Marculescu},
title = {Network-on-chip architectures and design methodologies},
journal = {Microprocess. Microsystems},
volume = {35},
number = {2},
pages = {83--84},
year = {2011},
url = {https://doi.org/10.1016/j.micpro.2011.01.002},
doi = {10.1016/J.MICPRO.2011.01.002},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mam/PalesiKM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PalesiAFC11,
author = {Maurizio Palesi and
Giuseppe Ascia and
Fabrizio Fazzino and
Vincenzo Catania},
title = {Data Encoding Schemes in Networks on Chip},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {5},
pages = {774--786},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2098590},
doi = {10.1109/TCAD.2010.2098590},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PalesiAFC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/Al-DujailyMXYP11,
author = {Ra'ed Al{-}Dujaily and
Terrence S. T. Mak and
Fei Xia and
Alexandre Yakovlev and
Maurizio Palesi},
title = {Run-time deadlock detection in networks-on-chip using coupled transitive
closure networks},
booktitle = {Design, Automation and Test in Europe, {DATE} 2011, Grenoble, France,
March 14-18, 2011},
pages = {497--502},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/DATE.2011.5763086},
doi = {10.1109/DATE.2011.5763086},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/Al-DujailyMXYP11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/npc/WangPYJHL11,
author = {Xiaohang Wang and
Maurizio Palesi and
Mei Yang and
Yingtao Jiang and
Michael C. Huang and
Peng Liu},
editor = {Erik R. Altman and
Weisong Shi},
title = {Power-Aware Run-Time Incremental Mapping for 3-D Networks-on-Chip},
booktitle = {Network and Parallel Computing - 8th {IFIP} International Conference,
{NPC} 2011, Changsha, China, October 21-23, 2011. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {6985},
pages = {232--247},
publisher = {Springer},
year = {2011},
url = {https://doi.org/10.1007/978-3-642-24403-2\_19},
doi = {10.1007/978-3-642-24403-2\_19},
timestamp = {Mon, 24 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/npc/WangPYJHL11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/WangPYJHL11,
author = {Xiaohang Wang and
Maurizio Palesi and
Mei Yang and
Yingtao Jiang and
Michael C. Huang and
Peng Liu},
title = {Low latency and energy efficient multicasting schemes for 3D NoC-based
SoCs},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {337--342},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081604},
doi = {10.1109/VLSISOC.2011.6081604},
timestamp = {Mon, 24 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/WangPYJHL11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@incollection{DBLP:books/sp/11/PalesiHKC11,
author = {Maurizio Palesi and
Rickard Holsmark and
Shashi Kumar and
Vincenzo Catania},
editor = {Cristina Silvano and
Marcello Lajolo and
Gianluca Palermo},
title = {Application-Specific Routing Algorithms for Low Power Network on Chip
Design},
booktitle = {Low Power Networks-on-Chip},
pages = {113--150},
publisher = {Springer},
year = {2011},
url = {https://doi.org/10.1007/978-1-4419-6911-8\_5},
doi = {10.1007/978-1-4419-6911-8\_5},
timestamp = {Fri, 02 Nov 2018 09:27:05 +0100},
biburl = {https://dblp.org/rec/books/sp/11/PalesiHKC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/micro/2011nocarc,
editor = {Maurizio Palesi and
Shashi Kumar},
title = {4th International Workshop on Network on Chip Architectures, NoCArc
'11, Porto Alegre, Brazil, December 4-5, 2011},
publisher = {{ACM}},
year = {2011},
url = {http://dl.acm.org/citation.cfm?id=2076501},
isbn = {978-1-4503-0947-9},
timestamp = {Thu, 02 Jan 2014 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/micro/2011nocarc.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PalesiKC10,
author = {Maurizio Palesi and
Shashi Kumar and
Vincenzo Catania},
title = {Leveraging Partially Faulty Links Usage for Enhancing Yield and Performance
in Networks-on-Chip},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {3},
pages = {426--440},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2041851},
doi = {10.1109/TCAD.2010.2041851},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PalesiKC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/PalesiHWKYJC10,
author = {Maurizio Palesi and
Rickard Holsmark and
Xiaohang Wang and
Shashi Kumar and
Mei Yang and
Yingtao Jiang and
Vincenzo Catania},
editor = {Sebasti{\'{a}}n L{\'{o}}pez},
title = {An Efficient Technique for In-order Packet Delivery with Adaptive
Routing Algorithms in Networks on Chip},
booktitle = {13th Euromicro Conference on Digital System Design, Architectures,
Methods and Tools, {DSD} 2010, 1-3 September 2010, Lille, France},
pages = {37--44},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/DSD.2010.53},
doi = {10.1109/DSD.2010.53},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/PalesiHWKYJC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/europar/HolsmarkKP10,
author = {Rickard Holsmark and
Shashi Kumar and
Maurizio Palesi},
editor = {Mario R. Guarracino and
Fr{\'{e}}d{\'{e}}ric Vivien and
Jesper Larsson Tr{\"{a}}ff and
Mario Cannataro and
Marco Danelutto and
Anders Hast and
Francesca Perla and
Andreas Kn{\"{u}}pfer and
Beniamino Di Martino and
Michael Alexander},
title = {A Multi-level Routing Scheme and Router Architecture to Support Hierarchical
Routing in Large Network on Chip Platforms},
booktitle = {Euro-Par 2010 Parallel Processing Workshops - HeteroPar, HPCC, HiBB,
CoreGrid, UCHPC, HPCF, PROPER, CCPI, VHPC, Ischia, Italy, August 31-September
3, 2010, Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {6586},
pages = {153--161},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-21878-1\_19},
doi = {10.1007/978-3-642-21878-1\_19},
timestamp = {Wed, 19 Feb 2020 14:52:57 +0100},
biburl = {https://dblp.org/rec/conf/europar/HolsmarkKP10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/micro/2010nocarc,
editor = {Maurizio Palesi and
Shashi Kumar and
Zhonghai Lu and
{\"{U}}mit Y. Ogras},
title = {Third International Workshop on Network on Chip Architectures, NoCArc'10,
Atlanta, GA, USA, December 4, 2010},
publisher = {{ACM}},
year = {2010},
url = {http://dl.acm.org/citation.cfm?id=1921249},
isbn = {978-1-4503-0397-2},
timestamp = {Thu, 02 Jan 2014 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/micro/2010nocarc.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/PalesiKC09,
author = {Maurizio Palesi and
Shashi Kumar and
Vincenzo Catania},
title = {Bandwidth-aware routing algorithms for networks-on-chip platforms},
journal = {{IET} Comput. Digit. Tech.},
volume = {3},
number = {5},
pages = {413--429},
year = {2009},
url = {https://doi.org/10.1049/iet-cdt.2008.0082},
doi = {10.1049/IET-CDT.2008.0082},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/PalesiKC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tpds/PalesiHKC09,
author = {Maurizio Palesi and
Rickard Holsmark and
Shashi Kumar and
Vincenzo Catania},
title = {Application Specific Routing Algorithms for Networks on Chip},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {20},
number = {3},
pages = {316--330},
year = {2009},
url = {https://doi.org/10.1109/TPDS.2008.106},
doi = {10.1109/TPDS.2008.106},
timestamp = {Fri, 02 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tpds/PalesiHKC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MejiaPFKLHD09,
author = {Andres Mejia and
Maurizio Palesi and
Jos{\'{e}} Flich and
Shashi Kumar and
Pedro L{\'{o}}pez and
Rickard Holsmark and
Jos{\'{e}} Duato},
title = {Region-Based Routing: {A} Mechanism to Support Efficient Routing Algorithms
in NoCs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {17},
number = {3},
pages = {356--369},
year = {2009},
url = {https://doi.org/10.1109/TVLSI.2008.2012010},
doi = {10.1109/TVLSI.2008.2012010},
timestamp = {Mon, 18 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MejiaPFKLHD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/PalesiFAC09,
author = {Maurizio Palesi and
Fabrizio Fazzino and
Giuseppe Ascia and
Vincenzo Catania},
editor = {Antonio N{\'{u}}{\~{n}}ez and
Pedro P. Carballo},
title = {Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip},
booktitle = {12th Euromicro Conference on Digital System Design, Architectures,
Methods and Tools, {DSD} 2009, 27-29 August 2009, Patras, Greece},
pages = {119--126},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/DSD.2009.203},
doi = {10.1109/DSD.2009.203},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/PalesiFAC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/CataniaNPPM09,
author = {Vincenzo Catania and
Alessandro G. Di Nuovo and
Maurizio Palesi and
Davide Patti and
Gianmarco De Francisci Morales},
editor = {Antonio N{\'{u}}{\~{n}}ez and
Pedro P. Carballo},
title = {An Effective Methodology to Multi-objective Design of Application
Domain-specific Embedded Architectures},
booktitle = {12th Euromicro Conference on Digital System Design, Architectures,
Methods and Tools, {DSD} 2009, 27-29 August 2009, Patras, Greece},
pages = {643--650},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/DSD.2009.205},
doi = {10.1109/DSD.2009.205},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/CataniaNPPM09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/TorneroSPO09,
author = {Rafael Tornero and
Valentino Sterrantino and
Maurizio Palesi and
Juan M. Ordu{\~{n}}a},
title = {A multi-objective strategy for concurrent mapping and routing in networks
on chip},
booktitle = {23rd {IEEE} International Symposium on Parallel and Distributed Processing,
{IPDPS} 2009, Rome, Italy, May 23-29, 2009},
pages = {1--8},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/IPDPS.2009.5161128},
doi = {10.1109/IPDPS.2009.5161128},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ipps/TorneroSPO09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nocs/HolsmarkKPM09,
author = {Rickard Holsmark and
Shashi Kumar and
Maurizio Palesi and
Andres Mejia},
title = {HiRA: {A} methodology for deadlock free routing in hierarchical networks
on chip},
booktitle = {Third International Symposium on Networks-on-Chips, {NOCS} 2009, May
10-13 2009, La Jolla, CA, {USA.} Proceedings},
pages = {2--11},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/NOCS.2009.5071439},
doi = {10.1109/NOCS.2009.5071439},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/nocs/HolsmarkKPM09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/micro/2009nocarc,
editor = {Maurizio Palesi and
Shashi Kumar},
title = {Second International Workshop on Network on Chip Architectures, NoCArc
2009, In conjunction with the 42nd Annual {IEEE/ACM} International
Symposium on Microarchitecture (MICRO-42), December 12, 2009, New
York, NY, {USA}},
publisher = {{ACM}},
year = {2009},
url = {http://dl.acm.org/citation.cfm?id=1645213},
isbn = {978-1-60558-774-5},
timestamp = {Wed, 13 Feb 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/micro/2009nocarc.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/HolsmarkPK08,
author = {Rickard Holsmark and
Maurizio Palesi and
Shashi Kumar},
title = {Deadlock free routing algorithms for irregular mesh topology NoC systems
with rectangular regions},
journal = {J. Syst. Archit.},
volume = {54},
number = {3-4},
pages = {427--440},
year = {2008},
url = {https://doi.org/10.1016/j.sysarc.2007.07.005},
doi = {10.1016/J.SYSARC.2007.07.005},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/HolsmarkPK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/CataniaPP08,
author = {Vincenzo Catania and
Maurizio Palesi and
Davide Patti},
title = {Reducing complexity of multiobjective design space exploration in
VLIW-based embedded systems},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {5},
number = {2},
pages = {11:1--11:33},
year = {2008},
url = {https://doi.org/10.1145/1400112.1400116},
doi = {10.1145/1400112.1400116},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/CataniaPP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/AsciaCPP08,
author = {Giuseppe Ascia and
Vincenzo Catania and
Maurizio Palesi and
Davide Patti},
title = {Implementation and Analysis of a New Selection Strategy for Adaptive
Routing in Networks-on-Chip},
journal = {{IEEE} Trans. Computers},
volume = {57},
number = {6},
pages = {809--820},
year = {2008},
url = {https://doi.org/10.1109/TC.2008.38},
doi = {10.1109/TC.2008.38},
timestamp = {Thu, 08 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/AsciaCPP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/FrazzettaDPKC08,
author = {Dario Frazzetta and
Giuseppe Dimartino and
Maurizio Palesi and
Shashi Kumar and
Vincenzo Catania},
editor = {Luca Fanucci},
title = {Efficient Application Specific Routing Algorithms for NoC Systems
utilizing Partially Faulty Links},
booktitle = {11th Euromicro Conference on Digital System Design: Architectures,
Methods and Tools, {DSD} 2008, Parma, Italy, September 3-5, 2008},
pages = {18--25},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/DSD.2008.26},
doi = {10.1109/DSD.2008.26},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/FrazzettaDPKC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/CataniaMNPP08,
author = {Vincenzo Catania and
Gianmarco De Francisci Morales and
Alessandro G. Di Nuovo and
Maurizio Palesi and
Davide Patti},
editor = {Luca Fanucci},
title = {High Performance Computing for Embedded System Design: {A} Case Study},
booktitle = {11th Euromicro Conference on Digital System Design: Architectures,
Methods and Tools, {DSD} 2008, Parma, Italy, September 3-5, 2008},
pages = {656--659},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/DSD.2008.110},
doi = {10.1109/DSD.2008.110},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/CataniaMNPP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/europar/TorneroOPD08,
author = {Rafael Tornero and
Juan M. Ordu{\~{n}}a and
Maurizio Palesi and
Jos{\'{e}} Duato},
editor = {Emilio Luque and
Tom{\`{a}}s Margalef and
Domingo Benitez},
title = {A Communication-Aware Topological Mapping Technique for NoCs},
booktitle = {Euro-Par 2008 - Parallel Processing, 14th International Euro-Par Conference,
Las Palmas de Gran Canaria, Spain, August 26-29, 2008, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5168},
pages = {910--919},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-85451-7\_98},
doi = {10.1007/978-3-540-85451-7\_98},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/europar/TorneroOPD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nocs/PalesiLSHKC08,
author = {Maurizio Palesi and
Giuseppe Longo and
Salvatore Signorino and
Rickard Holsmark and
Shashi Kumar and
Vincenzo Catania},
title = {Design of Bandwidth Aware and Congestion Avoiding Efficient Routing
Algorithms for Networks-on-Chip Platforms},
booktitle = {Second International Symposium on Networks-on-Chips, {NOCS} 2008,
5-6 April 2008, Newcastle University, {UK.} Proceedings},
pages = {97--106},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.ieeecomputersociety.org/10.1109/NOCS.2008.31},
doi = {10.1109/NOCS.2008.31},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/nocs/PalesiLSHKC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcsc/CataniaPP07,
author = {Vincenzo Catania and
Maurizio Palesi and
Davide Patti},
title = {Analysis and Tools for the Design of {VLIW} Embedded Systems in a
Multi-Objective Scenario},
journal = {J. Circuits Syst. Comput.},
volume = {16},
number = {5},
pages = {819--846},
year = {2007},
url = {https://doi.org/10.1142/S0218126607003915},
doi = {10.1142/S0218126607003915},
timestamp = {Tue, 25 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jcsc/CataniaPP07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/AsciaCNPP07,
author = {Giuseppe Ascia and
Vincenzo Catania and
Alessandro G. Di Nuovo and
Maurizio Palesi and
Davide Patti},
title = {Efficient design space exploration for application specific systems-on-a-chip},
journal = {J. Syst. Archit.},
volume = {53},
number = {10},
pages = {733--750},
year = {2007},
url = {https://doi.org/10.1016/j.sysarc.2007.01.004},
doi = {10.1016/J.SYSARC.2007.01.004},
timestamp = {Tue, 19 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jsa/AsciaCNPP07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/BertozziKP07,
author = {Davide Bertozzi and
Shashi Kumar and
Maurizio Palesi},
title = {Networks-on-Chip: Emerging Research Topics and Novel Ideas},
journal = {{VLSI} Design},
volume = {2007},
pages = {26454:1--26454:3},
year = {2007},
url = {https://doi.org/10.1155/2007/26454},
doi = {10.1155/2007/26454},
timestamp = {Thu, 16 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/BertozziKP07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fuzzIEEE/NuovoPC07,
author = {Alessandro G. Di Nuovo and
Maurizio Palesi and
Vincenzo Catania},
title = {Multi-Objective Evolutionary Fuzzy Clustering for High-Dimensional
Problems},
booktitle = {{FUZZ-IEEE} 2007, {IEEE} International Conference on Fuzzy Systems,
Imperial College, London, UK, 23-26 July, 2007, Proceedings},
pages = {1--6},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/FUZZY.2007.4295660},
doi = {10.1109/FUZZY.2007.4295660},
timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fuzzIEEE/NuovoPC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/PalesiKHC07,
author = {Maurizio Palesi and
Shashi Kumar and
Rickard Holsmark and
Vincenzo Catania},
title = {Exploiting Communication Concurrency for Efficient Deadlock Free Routing
in Reconfigurable NoC Platforms},
booktitle = {21th International Parallel and Distributed Processing Symposium {(IPDPS}
2007), Proceedings, 26-30 March 2007, Long Beach, California, {USA}},
pages = {1--8},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/IPDPS.2007.370367},
doi = {10.1109/IPDPS.2007.370367},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ipps/PalesiKHC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jucs/AsciaCP06,
author = {Giuseppe Ascia and
Vincenzo Catania and
Maurizio Palesi},
title = {A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip},
journal = {J. Univers. Comput. Sci.},
volume = {12},
number = {4},
pages = {370--394},
year = {2006},
url = {https://doi.org/10.3217/jucs-012-04-0370},
doi = {10.3217/JUCS-012-04-0370},
timestamp = {Thu, 07 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jucs/AsciaCP06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cec/AsciaCNPP06,
author = {Giuseppe Ascia and
Vincenzo Catania and
Alessandro G. Di Nuovo and
Maurizio Palesi and
Davide Patti},
title = {A Multiobjective Genetic Fuzzy Approach for Intelligent System-level
Exploration in Parameterized {VLIW} Processor Design},
booktitle = {{IEEE} International Conference on Evolutionary Computation, {CEC}
2006, part of {WCCI} 2006, Vancouver, BC, Canada, 16-21 July 2006},
pages = {1736--1743},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/CEC.2006.1688517},
doi = {10.1109/CEC.2006.1688517},
timestamp = {Thu, 16 Dec 2021 14:00:41 +0100},
biburl = {https://dblp.org/rec/conf/cec/AsciaCNPP06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/PalesiHKC06,
author = {Maurizio Palesi and
Rickard Holsmark and
Shashi Kumar and
Vincenzo Catania},
editor = {Reinaldo A. Bergamaschi and
Kiyoung Choi},
title = {A methodology for design of application specific deadlock-free routing
algorithms for NoC systems},
booktitle = {Proceedings of the 4th International Conference on Hardware/Software
Codesign and System Synthesis, {CODES+ISSS} 2006, Seoul, Korea, October
22-25, 2006},
pages = {142--147},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1176254.1176289},
doi = {10.1145/1176254.1176289},
timestamp = {Mon, 26 Nov 2018 12:14:45 +0100},
biburl = {https://dblp.org/rec/conf/codes/PalesiHKC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/NuovoPPAC06,
author = {Alessandro G. Di Nuovo and
Maurizio Palesi and
Davide Patti and
Giuseppe Ascia and
Vincenzo Catania},
editor = {Reinaldo A. Bergamaschi and
Kiyoung Choi},
title = {Fuzzy decision making in embedded system design},
booktitle = {Proceedings of the 4th International Conference on Hardware/Software
Codesign and System Synthesis, {CODES+ISSS} 2006, Seoul, Korea, October
22-25, 2006},
pages = {223--228},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1176254.1176309},
doi = {10.1145/1176254.1176309},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/codes/NuovoPPAC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/HolsmarkPK06,
author = {Rickard Holsmark and
Maurizio Palesi and
Shashi Kumar},
title = {Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with
Regions},
booktitle = {Ninth Euromicro Conference on Digital System Design: Architectures,
Methods and Tools {(DSD} 2006), 30 August - 1 September 2006, Dubrovnik,
Croatia},
pages = {696--703},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/DSD.2006.36},
doi = {10.1109/DSD.2006.36},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/HolsmarkPK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/estimedia/AsciaCPP06,
author = {Giuseppe Ascia and
Vincenzo Catania and
Maurizio Palesi and
Davide Patti},
editor = {Soonhoi Ha and
Samarjit Chakraborty},
title = {Neighbors-on-Path: {A} New Selection Strategy for On-Chip Networks},
booktitle = {Proceedings of the 2006 4th Workshop on Embedded Systems for Real-Time
Multimedia, ESTIMedia 2006, October 26-27, 2006, Seoul, Korea, conjunction
with {CODES+ISSS} 2006},
pages = {79--84},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/ESTMED.2006.321278},
doi = {10.1109/ESTMED.2006.321278},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/estimedia/AsciaCPP06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/samos/AsciaCNPP06,
author = {Giuseppe Ascia and
Vincenzo Catania and
Alessandro G. Di Nuovo and
Maurizio Palesi and
Davide Patti},
editor = {Georgi Gaydadjiev and
C. John Glossner and
Jarmo Takala and
Stamatis Vassiliadis},
title = {An Efficent Hierachical Fuzzy Approach for System Level System-on-a-Chip
Design},
booktitle = {Proceedings of 2006 International Conference on Embedded Computer
Systems: Architectures, Modeling and Simulation {(IC-SAMOS} 2006),
Samos, Greece, July 17-20, 2006},
pages = {115--122},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ICSAMOS.2006.300817},
doi = {10.1109/ICSAMOS.2006.300817},
timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/samos/AsciaCNPP06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/samos/PalesiKH06,
author = {Maurizio Palesi and
Shashi Kumar and
Rickard Holsmark},
editor = {Stamatis Vassiliadis and
Stephan Wong and
Timo H{\"{a}}m{\"{a}}l{\"{a}}inen},
title = {A Method for Router Table Compression for Application Specific Routing
in Mesh Topology NoC Architectures},
booktitle = {Embedded Computer Systems: Architectures, Modeling, and Simulation,
6th International Workshop, {SAMOS} 2006, Samos, Greece, July 17-20,
2006, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4017},
pages = {373--384},
publisher = {Springer},
year = {2006},
url = {https://doi.org/10.1007/11796435\_38},
doi = {10.1007/11796435\_38},
timestamp = {Tue, 14 May 2019 10:00:45 +0200},
biburl = {https://dblp.org/rec/conf/samos/PalesiKH06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/stairs/NuovoPP06,
author = {Alessandro G. Di Nuovo and
Maurizio Palesi and
Davide Patti},
editor = {Loris Penserini and
Pavlos Peppas and
Anna Perini},
title = {An Hybrid Soft Computing Approach for Automated Computer Design},
booktitle = {{STAIRS} 2006 - Proceedings of the Third Starting {AI} Researchers'
Symposium, Riva del Garda, Trentino, Italy, 2006},
series = {Frontiers in Artificial Intelligence and Applications},
volume = {142},
pages = {84--95},
publisher = {{IOS} Press},
year = {2006},
url = {http://www.booksonline.iospress.nl/Content/View.aspx?piid=1872},
timestamp = {Tue, 13 Mar 2012 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/stairs/NuovoPP06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AsciaCP05,
author = {Giuseppe Ascia and
Vincenzo Catania and
Maurizio Palesi},
title = {A multiobjective genetic approach for system-level exploration in
parameterized systems-on-a-chip},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {24},
number = {4},
pages = {635--645},
year = {2005},
url = {https://doi.org/10.1109/TCAD.2005.844118},
doi = {10.1109/TCAD.2005.844118},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AsciaCP05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asap/AsciaCPP05,
author = {Giuseppe Ascia and
Vincenzo Catania and
Maurizio Palesi and
Davide Patti},
title = {Exploring Design Space of {VLIW} Architectures},
booktitle = {16th {IEEE} International Conference on Application-Specific Systems,
Architectures, and Processors {(ASAP} 2005), 23-25 July 2005, Samos,
Greece},
pages = {86--91},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ASAP.2005.33},
doi = {10.1109/ASAP.2005.33},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asap/AsciaCPP05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/AsciaCPP05,
author = {Giuseppe Ascia and
Vincenzo Catania and
Maurizio Palesi and
Davide Patti},
editor = {Tingao Tang},
title = {A system-level framework for evaluating area/performance/power trade-offs
of VLIW-based embedded systems},
booktitle = {Proceedings of the 2005 Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2005, Shanghai, China, January 18-21, 2005},
pages = {940--943},
publisher = {{ACM} Press},
year = {2005},
url = {https://doi.org/10.1145/1120725.1120762},
doi = {10.1145/1120725.1120762},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/AsciaCPP05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cec/AsciaCP05,
author = {Giuseppe Ascia and
Vincenzo Catania and
Maurizio Palesi},
title = {An evolutionary approach to network-on-chip mapping problem},
booktitle = {Proceedings of the {IEEE} Congress on Evolutionary Computation, {CEC}
2005, 2-4 September 2005, Edinburgh, {UK}},
pages = {112--119},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/CEC.2005.1554674},
doi = {10.1109/CEC.2005.1554674},
timestamp = {Thu, 16 Dec 2021 13:59:05 +0100},
biburl = {https://dblp.org/rec/conf/cec/AsciaCP05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/AsciaCPP05,
author = {Giuseppe Ascia and
Vincenzo Catania and
Maurizio Palesi and
Davide Patti},
title = {Hyperblock formation: a power/energy perspective for high performance
{VLIW} architectures},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26
May 2005, Kobe, Japan},
pages = {4090--4093},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/ISCAS.2005.1465530},
doi = {10.1109/ISCAS.2005.1465530},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/AsciaCPP05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tec/AsciaCP04,
author = {Giuseppe Ascia and
Vincenzo Catania and
Maurizio Palesi},
title = {A GA-based design space exploration framework for parameterized system-on-a-chip
platforms},
journal = {{IEEE} Trans. Evol. Comput.},
volume = {8},
number = {4},
pages = {329--346},
year = {2004},
url = {https://doi.org/10.1109/TEVC.2004.826389},
doi = {10.1109/TEVC.2004.826389},
timestamp = {Tue, 12 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tec/AsciaCP04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/AsciaCP04,
author = {Giuseppe Ascia and
Vincenzo Catania and
Maurizio Palesi},
editor = {Alex Orailoglu and
Pai H. Chou and
Petru Eles and
Axel Jantsch},
title = {Multi-objective mapping for mesh-based NoC architectures},
booktitle = {Proceedings of the 2nd {IEEE/ACM/IFIP} International Conference on
Hardware/Software Codesign and System Synthesis, {CODES+ISSS} 2004,
Stockholm, Sweden, September 8-10, 2004},
pages = {182--187},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/1016720.1016765},
doi = {10.1145/1016720.1016765},
timestamp = {Wed, 04 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/codes/AsciaCP04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/eh/AsciaCPP04,
author = {Giuseppe Ascia and
Vincenzo Catania and
Maurizio Palesi and
Davide Patti},
title = {Multi-objective Optimization of a Parameterized {VLIW} Architecture},
booktitle = {6th {NASA} / DoD Workshop on Evolvable Hardware {(EH} 2004), 24-26
June 2004, Seattle, WA, {USA}},
pages = {191--198},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/EH.2004.1310830},
doi = {10.1109/EH.2004.1310830},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/eh/AsciaCPP04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cec/AsciaCPP03,
author = {Giuseppe Ascia and
Vincenzo Catania and
Maurizio Palesi and
Antonio Parlato},
title = {An evolutionary approach for reducing the switching activity in address
buses},
booktitle = {Proceedings of the {IEEE} Congress on Evolutionary Computation, {CEC}
2003, Canberra, Australia, December 8-12, 2003},
pages = {107--114},
publisher = {{IEEE}},
year = {2003},
url = {https://doi.org/10.1109/CEC.2003.1299563},
doi = {10.1109/CEC.2003.1299563},
timestamp = {Thu, 16 Dec 2021 11:43:24 +0100},
biburl = {https://dblp.org/rec/conf/cec/AsciaCPP03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/estimedia/AsciaCPP03,
author = {Giuseppe Ascia and
Vincenzo Catania and
Maurizio Palesi and
Davide Patti},
editor = {Gerhard Fohler and
Radu Marculescu},
title = {EPIC-Explorer: {A} Parameterized VLIW-based Platform Framework for
Design Space Exploration},
booktitle = {First Workshop on Embedded Systems for Real-Time Multimedia, ESTIMedia
2003, October 3-4, 2003, Newport Beach, California, USA, co-located
with {CODES-ISSS} 2003, Proceedings},
pages = {65--72},
year = {2003},
timestamp = {Thu, 17 Feb 2022 09:36:08 +0100},
biburl = {https://dblp.org/rec/conf/estimedia/AsciaCPP03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isict/AsciaCPP03,
author = {Giuseppe Ascia and
Vincenzo Catania and
Maurizio Palesi and
Antonio Parlato},
title = {An evolutionary approach for reducing the energy in address buses},
booktitle = {Proceedings of the 1st Intenational Symposium on Information and Communication
Technologies, Dublin, Ireland, September 24-26, 2003},
series = {{ACM} International Conference Proceeding Series},
volume = {49},
pages = {76--81},
publisher = {Trinity College Dublin},
year = {2003},
url = {https://dl.acm.org/citation.cfm?id=963615},
timestamp = {Mon, 26 Nov 2018 17:05:49 +0100},
biburl = {https://dblp.org/rec/conf/isict/AsciaCPP03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/AsciaCP03,
author = {Giuseppe Ascia and
Vincenzo Catania and
Maurizio Palesi},
editor = {Jorge Juan{-}Chico and
Enrico Macii},
title = {A Genetic Bus Encoding Technique for Power Optimization of Embedded
Systems},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation, 13th International Workshop, {PATMOS} 2003, Torino,
Italy, September 10-12, 2003, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {2799},
pages = {21--30},
publisher = {Springer},
year = {2003},
url = {https://doi.org/10.1007/978-3-540-39762-5\_4},
doi = {10.1007/978-3-540-39762-5\_4},
timestamp = {Tue, 14 May 2019 10:00:54 +0200},
biburl = {https://dblp.org/rec/conf/patmos/AsciaCP03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AsciaCP03,
author = {Giuseppe Ascia and
Vincenzo Catania and
Maurizio Palesi},
editor = {Manfred Glesner and
Ricardo Augusto da Luz Reis and
Hans Eveking and
Vincent John Mooney III and
Leandro Soares Indrusiak and
Peter Zipf},
title = {A Genetic Approach To Bus Encoding},
booktitle = {{IFIP} VLSI-SoC 2003, {IFIP} {WG} 10.5 International Conference on
Very Large Scale Integration of System-on-Chip, Darmstadt, Germany,
1-3 December 2003},
pages = {426--431},
publisher = {Technische Universit{\"{a}}t Darmstadt, Insitute of Microelectronic
Systems},
year = {2003},
timestamp = {Thu, 07 Oct 2004 09:29:26 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AsciaCP03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/PalesiG02,
author = {Maurizio Palesi and
Tony Givargis},
editor = {J{\"{o}}rg Henkel and
Xiaobo Sharon Hu and
Rajesh Gupta and
Sri Parameswaran},
title = {Multi-objective design space exploration using genetic algorithms},
booktitle = {Proceedings of the Tenth International Symposium on Hardware/Software
Codesign, {CODES} 2002, Estes Park, Colorado, USA, May 6-8, 2002},
pages = {67--72},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/774789.774804},
doi = {10.1145/774789.774804},
timestamp = {Mon, 09 Aug 2021 14:54:01 +0200},
biburl = {https://dblp.org/rec/conf/codes/PalesiG02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/AsciaCP02,
author = {Giuseppe Ascia and
Vincenzo Catania and
Maurizio Palesi},
title = {A Framework for Design Space Exploration of Parameterized {VLSI} Systems},
booktitle = {Proceedings of the 7th Asia and South Pacific Design Automation Conference
{(ASP-DAC} 2002), and the 15th International Conference on {VLSI}
Design {(VLSI} Design 2002), Bangalore, India, January 7-11, 2002},
pages = {245--250},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/ASPDAC.2002.994930},
doi = {10.1109/ASPDAC.2002.994930},
timestamp = {Mon, 14 Nov 2022 15:28:09 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/AsciaCP02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/AsciaCPS01,
author = {Giuseppe Ascia and
Vincenzo Catania and
Maurizio Palesi and
Davide Sarta},
title = {An Instruction-Level Power Analysis Model with Data Dependency},
journal = {{VLSI} Design},
volume = {12},
number = {2},
pages = {245--273},
year = {2001},
url = {https://doi.org/10.1155/2001/82129},
doi = {10.1155/2001/82129},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/AsciaCPS01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/AsciaCP01,
author = {Giuseppe Ascia and
Vincenzo Catania and
Maurizio Palesi},
editor = {Jan Madsen and
J{\"{o}}rg Henkel and
Xiaobo Sharon Hu},
title = {Parameterised system design based on genetic algorithms},
booktitle = {Proceedings of the Ninth International Symposium on Hardware/Software
Codesign, {CODES} 2001, Copenhagen, Denmark, 2001},
pages = {177--182},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/371636.371714},
doi = {10.1145/371636.371714},
timestamp = {Mon, 09 Aug 2021 14:54:01 +0200},
biburl = {https://dblp.org/rec/conf/codes/AsciaCP01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ifip10-5/AsciaCP01,
author = {Giuseppe Ascia and
Vincenzo Catania and
Maurizio Palesi},
editor = {Michel Robert and
Bruno Rouzeyre and
Christian Piguet and
Marie{-}Lise Flottes},
title = {An Evolutionary Approach for Pareto-optimal Configurations in {SOC}
Platforms},
booktitle = {{SOC} Design Methodologies, {IFIP} {TC10/WG10.5} Eleventh International
Conference on Very Large Scale Integration of Systems-on/Chip (VLSI-SOC'01),
December 3-5, 2001, Montpellier, France},
series = {{IFIP} Conference Proceedings},
volume = {218},
pages = {157--168},
publisher = {Kluwer},
year = {2001},
timestamp = {Tue, 13 Aug 2002 16:01:37 +0200},
biburl = {https://dblp.org/rec/conf/ifip10-5/AsciaCP01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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