BibTeX records: Gregory S. Still

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@article{DBLP:journals/jssc/VanderpoolRFSCC23,
  author       = {Brian T. Vanderpool and
                  Phillip J. Restle and
                  Eric Fluhr and
                  Gregory S. Still and
                  Francesco A. Campisano and
                  Ian Charmichael and
                  Eric Marz and
                  Rahul Batra and
                  Richard L. Willaman},
  title        = {Deterministic Frequency and Voltage Enhancements on the {POWER10}
                  Processor},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {58},
  number       = {1},
  pages        = {102--110},
  year         = {2023},
  url          = {https://doi.org/10.1109/JSSC.2022.3225378},
  doi          = {10.1109/JSSC.2022.3225378},
  timestamp    = {Sun, 15 Jan 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/jssc/VanderpoolRFSCC23.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/VanderpoolRFSCC22,
  author       = {Brian T. Vanderpool and
                  Phillip J. Restle and
                  Eric J. Fluhr and
                  Gregory S. Still and
                  Frank Campisano and
                  Ian Carmichael and
                  Eric Marz and
                  Rahul Batra and
                  Richard L. Willaman},
  title        = {Deterministic Frequency Boost and Voltage Enhancements on the POWER10\({}^{\mbox{TM}}\)
                  Processor},
  booktitle    = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2022,
                  San Francisco, CA, USA, February 20-26, 2022},
  pages        = {1--3},
  publisher    = {{IEEE}},
  year         = {2022},
  url          = {https://doi.org/10.1109/ISSCC42614.2022.9731746},
  doi          = {10.1109/ISSCC42614.2022.9731746},
  timestamp    = {Mon, 21 Mar 2022 13:32:47 +0100},
  biburl       = {https://dblp.org/rec/conf/isscc/VanderpoolRFSCC22.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ibmrd/ZyubanFDPPRDZCI15,
  author       = {Victor V. Zyuban and
                  Joshua Friedrich and
                  Daniel M. Dreps and
                  J{\"{u}}rgen Pille and
                  Donald W. Plass and
                  Phillip J. Restle and
                  Zeynep Toprak Deniz and
                  Matthew M. Ziegler and
                  Sam G. Chu and
                  Md. Saiful Islam and
                  James D. Warnock and
                  Bob Philhower and
                  Rahul M. Rao and
                  Gregory S. Still and
                  David Shan and
                  Eric Fluhr and
                  Jose Paredes and
                  Dieter F. Wendel and
                  Christopher J. Gonzalez and
                  D. Hogenmiller and
                  Ruchir Puri and
                  Scott A. Taylor and
                  Stephen D. Posluszny},
  title        = {{IBM} {POWER8} circuit design and energy optimization},
  journal      = {{IBM} J. Res. Dev.},
  volume       = {59},
  number       = {1},
  year         = {2015},
  url          = {https://doi.org/10.1147/JRD.2014.2380200},
  doi          = {10.1147/JRD.2014.2380200},
  timestamp    = {Fri, 13 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/ibmrd/ZyubanFDPPRDZCI15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/FluhrBBBDDEFGGGHJKMNPPPRRSSSSSDWWZ15,
  author       = {Eric J. Fluhr and
                  Steve Baumgartner and
                  David W. Boerstler and
                  John F. Bulzacchelli and
                  Timothy Diemoz and
                  Daniel Dreps and
                  George English and
                  Joshua Friedrich and
                  Anne Gattiker and
                  Tilman Gloekler and
                  Christopher J. Gonzalez and
                  Jason Hibbeler and
                  Keith A. Jenkins and
                  Yong Kim and
                  Paul Muench and
                  Ryan Nett and
                  Jose Paredes and
                  Juergen Pille and
                  Donald W. Plass and
                  Phillip J. Restle and
                  Raphael Robertazzi and
                  David Shan and
                  David W. Siljenberg and
                  Michael A. Sperling and
                  Kevin Stawiasz and
                  Gregory S. Still and
                  Zeynep Toprak Deniz and
                  James D. Warnock and
                  Glen A. Wiedemeier and
                  Victor V. Zyuban},
  title        = {The 12-Core POWER8{\texttrademark} Processor With 7.6 Tb/s {IO} Bandwidth,
                  Integrated Voltage Regulation, and Resonant Clocking},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {50},
  number       = {1},
  pages        = {10--23},
  year         = {2015},
  url          = {https://doi.org/10.1109/JSSC.2014.2358553},
  doi          = {10.1109/JSSC.2014.2358553},
  timestamp    = {Fri, 25 Feb 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/jssc/FluhrBBBDDEFGGGHJKMNPPPRRSSSSSDWWZ15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/icicdt/FriedrichLSSSFD14,
  author       = {Joshua Friedrich and
                  Hung Q. Le and
                  William J. Starke and
                  Jeff Stuecheli and
                  Balaram Sinharoy and
                  Eric J. Fluhr and
                  Daniel M. Dreps and
                  Victor V. Zyuban and
                  Gregory S. Still and
                  Christopher J. Gonzalez and
                  David Hogenmiller and
                  Frank Malgioglio and
                  Ryan Nett and
                  Ruchir Puri and
                  Phillip J. Restle and
                  David Shan and
                  Zeynep Toprak Deniz and
                  Dieter F. Wendel and
                  Matthew M. Ziegler and
                  Dave W. Victor},
  title        = {The POWER8\({}^{\mbox{TM}}\) processor: Designed for big data, analytics,
                  and cloud environments},
  booktitle    = {2014 {IEEE} International Conference on {IC} Design {\&} Technology,
                  {ICICDT} 2014, Austin, TX, USA, May 28-30, 2014},
  pages        = {1--4},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/ICICDT.2014.6838618},
  doi          = {10.1109/ICICDT.2014.6838618},
  timestamp    = {Fri, 25 Feb 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/icicdt/FriedrichLSSSFD14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/FluhrFDZSGHHMNP14,
  author       = {Eric J. Fluhr and
                  Joshua Friedrich and
                  Daniel M. Dreps and
                  Victor V. Zyuban and
                  Gregory S. Still and
                  Christopher J. Gonzalez and
                  Allen Hall and
                  David Hogenmiller and
                  Frank Malgioglio and
                  Ryan Nett and
                  Jose Paredes and
                  Juergen Pille and
                  Donald W. Plass and
                  Ruchir Puri and
                  Phillip J. Restle and
                  David Shan and
                  Kevin Stawiasz and
                  Zeynep Toprak Deniz and
                  Dieter F. Wendel and
                  Matthew M. Ziegler},
  title        = {5.1 POWER8\({}^{\mbox{TM}}\): {A} 12-core server-class processor in
                  22nm {SOI} with 7.6Tb/s off-chip bandwidth},
  booktitle    = {2014 {IEEE} International Conference on Solid-State Circuits Conference,
                  {ISSCC} 2014, Digest of Technical Papers, San Francisco, CA, USA,
                  February 9-13, 2014},
  pages        = {96--97},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/ISSCC.2014.6757353},
  doi          = {10.1109/ISSCC.2014.6757353},
  timestamp    = {Fri, 25 Feb 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isscc/FluhrFDZSGHHMNP14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/DenizSBSKKBGRSD14,
  author       = {Zeynep Toprak Deniz and
                  Michael A. Sperling and
                  John F. Bulzacchelli and
                  Gregory S. Still and
                  Ryan Kruse and
                  Seongwon Kim and
                  David Boerstler and
                  Tilman Gloekler and
                  Raphael Robertazzi and
                  Kevin Stawiasz and
                  Tim Diemoz and
                  George English and
                  David Hui and
                  Paul Muench and
                  Joshua Friedrich},
  title        = {5.2 Distributed system of digitally controlled microregulators enabling
                  per-core {DVFS} for the POWER8\({}^{\mbox{TM}}\) microprocessor},
  booktitle    = {2014 {IEEE} International Conference on Solid-State Circuits Conference,
                  {ISSCC} 2014, Digest of Technical Papers, San Francisco, CA, USA,
                  February 9-13, 2014},
  pages        = {98--99},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/ISSCC.2014.6757354},
  doi          = {10.1109/ISSCC.2014.6757354},
  timestamp    = {Mon, 10 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/DenizSBSKKBGRSD14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/RestleSHKDHBSJF14,
  author       = {Phillip J. Restle and
                  David Shan and
                  David Hogenmiller and
                  Yong Kim and
                  Alan J. Drake and
                  Jason Hibbeler and
                  Thomas J. Bucelot and
                  Gregory S. Still and
                  Keith A. Jenkins and
                  Joshua Friedrich},
  title        = {5.3 Wide-frequency-range resonant clock with on-the-fly mode changing
                  for the POWER8\({}^{\mbox{TM}}\) microprocessor},
  booktitle    = {2014 {IEEE} International Conference on Solid-State Circuits Conference,
                  {ISSCC} 2014, Digest of Technical Papers, San Francisco, CA, USA,
                  February 9-13, 2014},
  pages        = {100--101},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/ISSCC.2014.6757355},
  doi          = {10.1109/ISSCC.2014.6757355},
  timestamp    = {Fri, 25 Feb 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isscc/RestleSHKDHBSJF14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ibmrd/BishopCJMMPRSW96,
  author       = {James W. Bishop and
                  Michael J. Campion and
                  Thomas L. Jeremiah and
                  Stephen J. Mercier and
                  Edmond J. Mohring and
                  Kerry P. Pfarr and
                  Bruce G. Rudolph and
                  Gregory S. Still and
                  Tennis S. White},
  title        = {PowerPC {AS} {A10} 64-bit {RISC} microprocessor},
  journal      = {{IBM} J. Res. Dev.},
  volume       = {40},
  number       = {4},
  pages        = {495--506},
  year         = {1996},
  url          = {https://doi.org/10.1147/rd.404.0495},
  doi          = {10.1147/RD.404.0495},
  timestamp    = {Fri, 13 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/ibmrd/BishopCJMMPRSW96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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