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ORCIDBibTeX records: Shouyi Yin
@article{DBLP:journals/jssc/TuWWWLHWY24,
author = {Fengbin Tu and
Zihan Wu and
Yiqi Wang and
Weiwei Wu and
Leibo Liu and
Yang Hu and
Shaojun Wei and
Shouyi Yin},
title = {MulTCIM: Digital Computing-in-Memory-Based Multimodal Transformer
Accelerator With Attention-Token-Bit Hybrid Sparsity},
journal = {{IEEE} J. Solid State Circuits},
volume = {59},
number = {1},
pages = {90--101},
year = {2024},
url = {https://doi.org/10.1109/JSSC.2023.3305663},
doi = {10.1109/JSSC.2023.3305663},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/TuWWWLHWY24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/LiuXSZOY24,
author = {Dajiang Liu and
Yuxin Xia and
Jiaxing Shang and
Jiang Zhong and
Peng Ouyang and
Shouyi Yin},
title = {E2EMap: End-to-End Reinforcement Learning for {CGRA} Compilation via
Reverse Mapping},
booktitle = {{IEEE} International Symposium on High-Performance Computer Architecture,
{HPCA} 2024, Edinburgh, United Kingdom, March 2-6, 2024},
pages = {46--60},
publisher = {{IEEE}},
year = {2024},
url = {https://doi.org/10.1109/HPCA57654.2024.00015},
doi = {10.1109/HPCA57654.2024.00015},
timestamp = {Wed, 17 Apr 2024 17:17:11 +0200},
biburl = {https://dblp.org/rec/conf/hpca/LiuXSZOY24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/YueXTWWWHY24,
author = {Zhiheng Yue and
Xujiang Xiang and
Fengbin Tu and
Yang Wang and
Yiming Wang and
Shaojun Wei and
Yang Hu and
Shouyi Yin},
title = {15.1 {A} 0.795fJ/bit Physically-Unclonable Function-Protected {TCAM}
for a Software-Defined Networking Switch},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2024,
San Francisco, CA, USA, February 18-22, 2024},
pages = {276--278},
publisher = {{IEEE}},
year = {2024},
url = {https://doi.org/10.1109/ISSCC49657.2024.10454312},
doi = {10.1109/ISSCC49657.2024.10454312},
timestamp = {Tue, 19 Mar 2024 09:04:31 +0100},
biburl = {https://dblp.org/rec/conf/isscc/YueXTWWWHY24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/GuoWCSYQHWTWHY24,
author = {Ruiqi Guo and
Lei Wang and
Xiaofeng Chen and
Hao Sun and
Zhiheng Yue and
Yubin Qin and
Huiming Han and
Yang Wang and
Fengbin Tu and
Shaojun Wei and
Yang Hu and
Shouyi Yin},
title = {20.2 {A} 28nm 74.34TFLOPS/W {BF16} Heterogenous CIM-Based Accelerator
Exploiting Denoising-Similarity for Diffusion Models},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2024,
San Francisco, CA, USA, February 18-22, 2024},
pages = {362--364},
publisher = {{IEEE}},
year = {2024},
url = {https://doi.org/10.1109/ISSCC49657.2024.10454308},
doi = {10.1109/ISSCC49657.2024.10454308},
timestamp = {Tue, 19 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/GuoWCSYQHWTWHY24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/WangYQZGYHWHY24,
author = {Yang Wang and
Xiaolong Yang and
Yubin Qin and
Zhiren Zhao and
Ruiqi Guo and
Zhiheng Yue and
Huiming Han and
Shaojun Wei and
Yang Hu and
Shouyi Yin},
title = {34.1 {A} 28nm 83.23TFLOPS/W POSIT-Based Compute-in-Memory Macro for
High-Accuracy {AI} Applications},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2024,
San Francisco, CA, USA, February 18-22, 2024},
pages = {566--568},
publisher = {{IEEE}},
year = {2024},
url = {https://doi.org/10.1109/ISSCC49657.2024.10454567},
doi = {10.1109/ISSCC49657.2024.10454567},
timestamp = {Tue, 19 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/WangYQZGYHWHY24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ZhuZLZDCYYWL23,
author = {Yihong Zhu and
Wenping Zhu and
Chongyang Li and
Min Zhu and
Chenchen Deng and
Chen Chen and
Shuying Yin and
Shouyi Yin and
Shaojun Wei and
Leibo Liu},
title = {RePQC: {A} 3.4-uJ/Op 48-kOPS Post-Quantum Crypto-Processor for Multiple-Mathematical
Problems},
journal = {{IEEE} J. Solid State Circuits},
volume = {58},
number = {1},
pages = {124--140},
year = {2023},
url = {https://doi.org/10.1109/JSSC.2022.3216758},
doi = {10.1109/JSSC.2022.3216758},
timestamp = {Wed, 06 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/ZhuZLZDCYYWL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/WangQDWZFCSLWY23,
author = {Yang Wang and
Yubin Qin and
Dazheng Deng and
Jingchuan Wei and
Yang Zhou and
Yuanqi Fan and
Tianbao Chen and
Hao Sun and
Leibo Liu and
Shaojun Wei and
Shouyi Yin},
title = {An Energy-Efficient Transformer Processor Exploiting Dynamic Weak
Relevances in Global Attention},
journal = {{IEEE} J. Solid State Circuits},
volume = {58},
number = {1},
pages = {227--242},
year = {2023},
url = {https://doi.org/10.1109/JSSC.2022.3213521},
doi = {10.1109/JSSC.2022.3213521},
timestamp = {Sun, 15 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/WangQDWZFCSLWY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/TuWWLDKLWXY23,
author = {Fengbin Tu and
Yiqi Wang and
Zihan Wu and
Ling Liang and
Yufei Ding and
Bongjin Kim and
Leibo Liu and
Shaojun Wei and
Yuan Xie and
Shouyi Yin},
title = {ReDCIM: Reconfigurable Digital Computing- In -Memory Processor With
Unified {FP/INT} Pipeline for Cloud {AI} Acceleration},
journal = {{IEEE} J. Solid State Circuits},
volume = {58},
number = {1},
pages = {243--255},
year = {2023},
url = {https://doi.org/10.1109/JSSC.2022.3222059},
doi = {10.1109/JSSC.2022.3222059},
timestamp = {Sun, 15 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/TuWWLDKLWXY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/GuoYSLHTWSLCLWY23,
author = {Ruiqi Guo and
Zhiheng Yue and
Xin Si and
Hao Li and
Te Hu and
Limei Tang and
Yabing Wang and
Hao Sun and
Leibo Liu and
Meng{-}Fan Chang and
Qiang Li and
Shaojun Wei and
Shouyi Yin},
title = {TT@CIM: {A} Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity
Optimization and Variable Precision Quantization},
journal = {{IEEE} J. Solid State Circuits},
volume = {58},
number = {3},
pages = {852--866},
year = {2023},
url = {https://doi.org/10.1109/JSSC.2022.3198413},
doi = {10.1109/JSSC.2022.3198413},
timestamp = {Sat, 11 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/GuoYSLHTWSLCLWY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/Tu00L0DLW0Y23,
author = {Fengbin Tu and
Zihan Wu and
Yiqi Wang and
Ling Liang and
Liu Liu and
Yufei Ding and
Leibo Liu and
Shaojun Wei and
Yuan Xie and
Shouyi Yin},
title = {TranCIM: Full-Digital Bitline-Transpose CIM-based Sparse Transformer
Accelerator With Pipeline/Parallel Reconfigurable Modes},
journal = {{IEEE} J. Solid State Circuits},
volume = {58},
number = {6},
pages = {1798--1809},
year = {2023},
url = {https://doi.org/10.1109/JSSC.2022.3213542},
doi = {10.1109/JSSC.2022.3213542},
timestamp = {Thu, 15 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/Tu00L0DLW0Y23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TuWLDLWYX23,
author = {Fengbin Tu and
Yiqi Wang and
Ling Liang and
Yufei Ding and
Leibo Liu and
Shaojun Wei and
Shouyi Yin and
Yuan Xie},
title = {{SDP:} Co-Designing Algorithm, Dataflow, and Architecture for In-SRAM
Sparse {NN} Acceleration},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {42},
number = {1},
pages = {109--121},
year = {2023},
url = {https://doi.org/10.1109/TCAD.2022.3172600},
doi = {10.1109/TCAD.2022.3172600},
timestamp = {Sun, 15 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/TuWLDLWYX23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KouGYWY23,
author = {Mingyang Kou and
Jiangyuan Gu and
Hailong Yao and
Shaojun Wei and
Shouyi Yin},
title = {{TAEM} 2.0: {A} Faster Transfer-Aware Effective Loop Mapping for Heterogeneous
Resources on {CGRA}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {42},
number = {8},
pages = {2552--2565},
year = {2023},
url = {https://doi.org/10.1109/TCAD.2022.3226152},
doi = {10.1109/TCAD.2022.3226152},
timestamp = {Sat, 05 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KouGYWY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KongZMSHDGYWL23,
author = {Xiangyu Kong and
Jianfeng Zhu and
Xingchen Man and
Guihuan Song and
Yi Huang and
Chenchen Deng and
Pengfei Gou and
Shouyi Yin and
Shaojun Wei and
Leibo Liu},
title = {M2STaR: {A} Multimode Spatio-Temporal Redundancy Design for Fault-Tolerant
Coarse-Grained Reconfigurable Architectures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {42},
number = {9},
pages = {2938--2951},
year = {2023},
url = {https://doi.org/10.1109/TCAD.2023.3239563},
doi = {10.1109/TCAD.2023.3239563},
timestamp = {Thu, 14 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KongZMSHDGYWL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcasI/WangTLWXY23,
author = {Yiqi Wang and
Fengbin Tu and
Leibo Liu and
Shaojun Wei and
Yuan Xie and
Shouyi Yin},
title = {{SPCIM:} Sparsity-Balanced Practical {CIM} Accelerator With Optimized
Spatial-Temporal Multi-Macro Utilization},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {70},
number = {1},
pages = {214--227},
year = {2023},
url = {https://doi.org/10.1109/TCSI.2022.3216735},
doi = {10.1109/TCSI.2022.3216735},
timestamp = {Fri, 10 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcasI/WangTLWXY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcasI/WeiLTWLY23,
author = {Shaojun Wei and
Xinhan Lin and
Fengbin Tu and
Yang Wang and
Leibo Liu and
Shouyi Yin},
title = {Reconfigurability, Why It Matters in {AI} Tasks Processing: {A} Survey
of Reconfigurable {AI} Chips},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {70},
number = {3},
pages = {1228--1241},
year = {2023},
url = {https://doi.org/10.1109/TCSI.2022.3228860},
doi = {10.1109/TCSI.2022.3228860},
timestamp = {Sat, 11 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcasI/WeiLTWLY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcasI/WuTNYLWL0Y23,
author = {Weiwei Wu and
Fengbin Tu and
Mengqi Niu and
Zhiheng Yue and
Leibo Liu and
Shaojun Wei and
Xiangyu Li and
Yang Hu and
Shouyi Yin},
title = {{STAR:} An {STGCN} ARchitecture for Skeleton-Based Human Action Recognition},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {70},
number = {6},
pages = {2370--2383},
year = {2023},
url = {https://doi.org/10.1109/TCSI.2023.3254610},
doi = {10.1109/TCSI.2023.3254610},
timestamp = {Thu, 15 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcasI/WuTNYLWL0Y23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aicas/ChenGYHLWY23,
author = {Xiaofeng Chen and
Ruiqi Guo and
Zhiheng Yue and
Yang Hu and
Leibo Liu and
Shaojun Wei and
Shouyi Yin},
title = {A Systolic Computing-in-Memory Array based Accelerator with Predictive
Early Activation for Spatiotemporal Convolutions},
booktitle = {5th {IEEE} International Conference on Artificial Intelligence Circuits
and Systems, {AICAS} 2023, Hangzhou, China, June 11-13, 2023},
pages = {1--5},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/AICAS57966.2023.10168581},
doi = {10.1109/AICAS57966.2023.10168581},
timestamp = {Mon, 24 Jul 2023 15:56:17 +0200},
biburl = {https://dblp.org/rec/conf/aicas/ChenGYHLWY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aicas/WangWTHHLWY23,
author = {Zhou Wang and
Jingchuan Wei and
Xiaonan Tang and
Boxiao Han and
Hongjun He and
Leibo Liu and
Shaojun Wei and
Shouyi Yin},
title = {{TPE:} {A} High-Performance Edge-Device Inference with Multi-level
Transformational Mechanism},
booktitle = {5th {IEEE} International Conference on Artificial Intelligence Circuits
and Systems, {AICAS} 2023, Hangzhou, China, June 11-13, 2023},
pages = {1--5},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/AICAS57966.2023.10168614},
doi = {10.1109/AICAS57966.2023.10168614},
timestamp = {Mon, 24 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aicas/WangWTHHLWY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/GuoWCWSWLWHY23,
author = {Ruiqi Guo and
Yang Wang and
Xiaofeng Chen and
Lei Wang and
Hao Sun and
Jingchuan Wei and
Leibo Liu and
Shaojun Wei and
Yang Hu and
Shouyi Yin},
title = {CIMFormer: {A} 38.9TOPS/W-8b Systolic CIM-Array Based Transformer
Processor with Token-Slimmed Attention Reformulating and Principal
Possibility Gathering},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2023, Haikou,
China, November 5-8, 2023},
pages = {1--3},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/A-SSCC58667.2023.10347930},
doi = {10.1109/A-SSCC58667.2023.10347930},
timestamp = {Sat, 27 Jan 2024 20:22:56 +0100},
biburl = {https://dblp.org/rec/conf/asscc/GuoWCWSWLWHY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/QinWDYZZFWCLWHY23,
author = {Yubin Qin and
Yang Wang and
Dazheng Deng and
Xiaolong Yang and
Zhiren Zhao and
Yang Zhou and
Yuanqi Fan and
Jingchuan Wei and
Tianbao Chen and
Leibo Liu and
Shaojun Wei and
Yang Hu and
Shouyi Yin},
title = {A 28nm 49.7TOPS/W Sparse Transformer Processor with Random-Projection-Based
Speculation, Multi-Stationary Dataflow, and Redundant Partial Product
Elimination},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2023, Haikou,
China, November 5-8, 2023},
pages = {1--3},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/A-SSCC58667.2023.10347953},
doi = {10.1109/A-SSCC58667.2023.10347953},
timestamp = {Sat, 27 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asscc/QinWDYZZFWCLWHY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/LiuMZZSZY23,
author = {Dajiang Liu and
Di Mou and
Rong Zhu and
Yan Zhuang and
Jiaxing Shang and
Jiang Zhong and
Shouyi Yin},
title = {{DARIC:} {A} Data Reuse-Friendly {CGRA} for Parallel Data Access via
Elastic FIFOs},
booktitle = {60th {ACM/IEEE} Design Automation Conference, {DAC} 2023, San Francisco,
CA, USA, July 9-13, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/DAC56929.2023.10247862},
doi = {10.1109/DAC56929.2023.10247862},
timestamp = {Sun, 24 Sep 2023 13:31:06 +0200},
biburl = {https://dblp.org/rec/conf/dac/LiuMZZSZY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/WangWHHLWY23,
author = {Zhou Wang and
Jingchuan Wei and
Boxiao Han and
Hongjun He and
Leibo Liu and
Shaojun Wei and
Shouyi Yin},
title = {{CPE:} An Energy-Efficient Edge-Device Training with Multi-dimensional
Compression Mechanism},
booktitle = {60th {ACM/IEEE} Design Automation Conference, {DAC} 2023, San Francisco,
CA, USA, July 9-13, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/DAC56929.2023.10247968},
doi = {10.1109/DAC56929.2023.10247968},
timestamp = {Sun, 24 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/WangWHHLWY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/WuGLHHHLWY23,
author = {Qidie Wu and
Jiangyuan Gu and
Youxu Lin and
Boxiao Han and
Hongjun He and
Yang Hu and
Leibo Liu and
Shaojun Wei and
Shouyi Yin},
title = {{RMP-MEM:} {A} {HW/SW} Reconfigurable Multi-Port Memory Architecture
for Multi-PEA Oriented {CGRA}},
booktitle = {60th {ACM/IEEE} Design Automation Conference, {DAC} 2023, San Francisco,
CA, USA, July 9-13, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/DAC56929.2023.10247776},
doi = {10.1109/DAC56929.2023.10247776},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/WuGLHHHLWY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/QinWDZYLW0Y23,
author = {Yubin Qin and
Yang Wang and
Dazheng Deng and
Zhiren Zhao and
Xiaolong Yang and
Leibo Liu and
Shaojun Wei and
Yang Hu and
Shouyi Yin},
editor = {Yan Solihin and
Mark A. Heinrich},
title = {{FACT:} FFN-Attention Co-optimized Transformer Architecture with Eager
Correlation Prediction},
booktitle = {Proceedings of the 50th Annual International Symposium on Computer
Architecture, {ISCA} 2023, Orlando, FL, USA, June 17-21, 2023},
pages = {22:1--22:14},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3579371.3589057},
doi = {10.1145/3579371.3589057},
timestamp = {Tue, 11 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isca/QinWDZYLW0Y23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/YueWWWGTLWHY23,
author = {Zhiheng Yue and
Yang Wang and
Huizheng Wang and
Yabing Wang and
Ruiqi Guo and
Limei Tang and
Leibo Liu and
Shaojun Wei and
Yang Hu and
Shouyi Yin},
title = {{CV-CIM:} {A} 28nm XOR-Derived Similarity-Aware Computation-in-Memory
for Cost-Volume Construction},
booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2023,
San Francisco, CA, USA, February 19-23, 2023},
pages = {138--139},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISSCC42615.2023.10067720},
doi = {10.1109/ISSCC42615.2023.10067720},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/YueWWWGTLWHY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/TuWWWLHWY23,
author = {Fengbin Tu and
Zihan Wu and
Yiqi Wang and
Weiwei Wu and
Leibo Liu and
Yang Hu and
Shaojun Wei and
Shouyi Yin},
title = {MuITCIM: {A} 28nm {\textdollar}2.24 {\textbackslash}mu{\textbackslash}mathrm\{J\}{\textdollar}/Token
Attention-Token-Bit Hybrid Sparse Digital CIM-Based Accelerator for
Multimodal Transformers},
booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2023,
San Francisco, CA, USA, February 19-23, 2023},
pages = {248--249},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISSCC42615.2023.10067842},
doi = {10.1109/ISSCC42615.2023.10067842},
timestamp = {Fri, 02 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/TuWWWLHWY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/TuWWWLHWY23a,
author = {Fengbin Tu and
Yiqi Wang and
Zihan Wu and
Weiwei Wu and
Leibo Liu and
Yang Hu and
Shaojun Wei and
Shouyi Yin},
title = {TensorCIM: {A} 28nm 3.7nJ/Gather and 8.3TFLOPS/W {FP32} Digital-CIM
Tensor Processor for MCM-CIM-Based Beyond-NN Acceleration},
booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2023,
San Francisco, CA, USA, February 19-23, 2023},
pages = {254--255},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISSCC42615.2023.10067285},
doi = {10.1109/ISSCC42615.2023.10067285},
timestamp = {Thu, 30 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/TuWWWLHWY23a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/DengTZLZHHTLW0Y23,
author = {Jinyi Deng and
Xinru Tang and
Jiahao Zhang and
Yuxuan Li and
Linyun Zhang and
Boxiao Han and
Hongjun He and
Fengbin Tu and
Leibo Liu and
Shaojun Wei and
Yang Hu and
Shouyi Yin},
title = {Towards Efficient Control Flow Handling in Spatial Architecture via
Architecting the Control Flow Plane},
booktitle = {Proceedings of the 56th Annual {IEEE/ACM} International Symposium
on Microarchitecture, {MICRO} 2023, Toronto, ON, Canada, 28 October
2023 - 1 November 2023},
pages = {1395--1408},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3613424.3614246},
doi = {10.1145/3613424.3614246},
timestamp = {Sun, 31 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/micro/DengTZLZHHTLW0Y23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsit/WangQDYZGYLW0Y23,
author = {Yang Wang and
Yubin Qin and
Dazheng Deng and
Xiaolong Yang and
Zhiren Zhao and
Ruiqi Guo and
Zhiheng Yue and
Leibo Liu and
Shaojun Wei and
Yang Hu and
Shouyi Yin},
title = {A 28nm 77.35TOPS/W Similar Vectors Traceable Transformer Processor
with Principal-Component-Prior Speculating and Dynamic Bit-wise Stationary
Computing},
booktitle = {2023 {IEEE} Symposium on {VLSI} Technology and Circuits {(VLSI} Technology
and Circuits), Kyoto, Japan, June 11-16, 2023},
pages = {1--2},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185403},
doi = {10.23919/VLSITECHNOLOGYANDCIR57934.2023.10185403},
timestamp = {Fri, 28 Jul 2023 10:40:41 +0200},
biburl = {https://dblp.org/rec/conf/vlsit/WangQDYZGYLW0Y23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2305-10769,
author = {Shitong Shao and
Xu Dai and
Shouyi Yin and
Lujun Li and
Huanran Chen and
Yang Hu},
title = {Catch-Up Distillation: You Only Need to Train Once for Accelerating
Sampling},
journal = {CoRR},
volume = {abs/2305.10769},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2305.10769},
doi = {10.48550/ARXIV.2305.10769},
eprinttype = {arXiv},
eprint = {2305.10769},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2305-10769.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2307-02847,
author = {Jinyi Deng and
Xinru Tang and
Jiahao Zhang and
Yuxuan Li and
Linyun Zhang and
Fengbin Tu and
Leibo Liu and
Shaojun Wei and
Yang Hu and
Shouyi Yin},
title = {Towards Efficient Control Flow Handling in Spatial Architecture via
Architecting the Control Flow Plane},
journal = {CoRR},
volume = {abs/2307.02847},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2307.02847},
doi = {10.48550/ARXIV.2307.02847},
eprinttype = {arXiv},
eprint = {2307.02847},
timestamp = {Tue, 02 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2307-02847.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2309-01273,
author = {Haojia Hui and
Jiangyuan Gu and
Xunbo Hu and
Yang Hu and
Leibo Liu and
Shaojun Wei and
Shouyi Yin},
title = {WindMill: {A} Parameterized and Pluggable {CGRA} Implemented by {DIAG}
Design Flow},
journal = {CoRR},
volume = {abs/2309.01273},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2309.01273},
doi = {10.48550/ARXIV.2309.01273},
eprinttype = {arXiv},
eprint = {2309.01273},
timestamp = {Sun, 24 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2309-01273.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2310-09568,
author = {Yang Hu and
Xinhan Lin and
Huizheng Wang and
Zhen He and
Xingmao Yu and
Jiahao Zhang and
Qize Yang and
Zheng Xu and
Sihan Guan and
Jiahao Fang and
Haoran Shang and
Xinru Tang and
Xu Dai and
Shaojun Wei and
Shouyi Yin},
title = {Wafer-scale Computing: Advancements, Challenges, and Future Perspectives},
journal = {CoRR},
volume = {abs/2310.09568},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2310.09568},
doi = {10.48550/ARXIV.2310.09568},
eprinttype = {arXiv},
eprint = {2310.09568},
timestamp = {Wed, 25 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2310-09568.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/chinaf/DengZYWHYZYWL22,
author = {Chenchen Deng and
Min Zhu and
Jinjiang Yang and
Youyu Wu and
Jiaji He and
Bohan Yang and
Jianfeng Zhu and
Shouyi Yin and
Shaojun Wei and
Leibo Liu},
title = {An energy-efficient dynamically reconfigurable cryptographic engine
with improved power/EM-side-channel-attack resistance},
journal = {Sci. China Inf. Sci.},
volume = {65},
number = {4},
year = {2022},
url = {https://doi.org/10.1007/s11432-020-3206-2},
doi = {10.1007/S11432-020-3206-2},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/chinaf/DengZYWHYZYWL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/MoZHLLYWL22,
author = {Huiyu Mo and
Wenping Zhu and
Wenjing Hu and
Qiang Li and
Ang Li and
Shouyi Yin and
Shaojun Wei and
Leibo Liu},
title = {A 12.1 {TOPS/W} Quantized Network Acceleration Processor With Effective-Weight-Based
Convolution and Error-Compensation-Based Prediction},
journal = {{IEEE} J. Solid State Circuits},
volume = {57},
number = {5},
pages = {1542--1557},
year = {2022},
url = {https://doi.org/10.1109/JSSC.2021.3113569},
doi = {10.1109/JSSC.2021.3113569},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/MoZHLLYWL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChoiHYR22,
author = {Jung{-}Hwan Choi and
Po{-}Chiun Huang and
Shouyi Yin and
Woogeun Rhee},
title = {Guest Editorial Introduction to the Special Section on the 2021 Asian
Solid-State Circuits Conference {(A-SSCC)}},
journal = {{IEEE} J. Solid State Circuits},
volume = {57},
number = {10},
pages = {2895--2897},
year = {2022},
url = {https://doi.org/10.1109/JSSC.2022.3196310},
doi = {10.1109/JSSC.2022.3196310},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/ChoiHYR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/WangQDWCLLWY22,
author = {Yang Wang and
Yubin Qin and
Dazheng Deng and
Jingchuan Wei and
Tianbao Chen and
Xinhan Lin and
Leibo Liu and
Shaojun Wei and
Shouyi Yin},
title = {Trainer: An Energy-Efficient Edge-Device Training Processor Supporting
Dynamic Weight Pruning},
journal = {{IEEE} J. Solid State Circuits},
volume = {57},
number = {10},
pages = {3164--3178},
year = {2022},
url = {https://doi.org/10.1109/JSSC.2022.3174411},
doi = {10.1109/JSSC.2022.3174411},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/WangQDWCLLWY22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HouZ0W0YWL22,
author = {Zongsheng Hou and
Neng Zhang and
Bohan Yang and
Hanning Wang and
Min Zhu and
Shouyi Yin and
Shaojun Wei and
Leibo Liu},
title = {Efficient {FHE} Radix-2 Arithmetic Operations Based on Redundant Encoding},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {41},
number = {7},
pages = {2024--2037},
year = {2022},
url = {https://doi.org/10.1109/TCAD.2021.3101410},
doi = {10.1109/TCAD.2021.3101410},
timestamp = {Mon, 05 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/HouZ0W0YWL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YuanZMMYWL22,
author = {Baofen Yuan and
Jianfeng Zhu and
Xingchen Man and
Zijiao Ma and
Shouyi Yin and
Shaojun Wei and
Leibo Liu},
title = {Dynamic-II Pipeline: Compiling Loops With Irregular Branches on Static-Scheduling
{CGRA}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {41},
number = {9},
pages = {2929--2942},
year = {2022},
url = {https://doi.org/10.1109/TCAD.2021.3121346},
doi = {10.1109/TCAD.2021.3121346},
timestamp = {Sat, 10 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YuanZMMYWL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiMZLYWL22,
author = {Ang Li and
Huiyu Mo and
Wenping Zhu and
Qiang Li and
Shouyi Yin and
Shaojun Wei and
Leibo Liu},
title = {BitCluster: Fine-Grained Weight Quantization for Load-Balanced Bit-Serial
Neural Network Accelerators},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {41},
number = {11},
pages = {4747--4757},
year = {2022},
url = {https://doi.org/10.1109/TCAD.2022.3146202},
doi = {10.1109/TCAD.2022.3146202},
timestamp = {Tue, 08 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/LiMZLYWL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcasI/WuJMGLHYWL22,
author = {Yong Wu and
Honglan Jiang and
Zining Ma and
Pengfei Gou and
Yong Lu and
Jie Han and
Shouyi Yin and
Shaojun Wei and
Leibo Liu},
title = {An Energy-Efficient Approximate Divider Based on Logarithmic Conversion
and Piecewise Constant Approximation},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {69},
number = {7},
pages = {2655--2668},
year = {2022},
url = {https://doi.org/10.1109/TCSI.2022.3167894},
doi = {10.1109/TCSI.2022.3167894},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcasI/WuJMGLHYWL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcasI/YueWQLWY22,
author = {Zhiheng Yue and
Yabing Wang and
Yubin Qin and
Leibo Liu and
Shaojun Wei and
Shouyi Yin},
title = {{BR-CIM:} An Efficient Binary Representation Computation-In-Memory
Design},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {69},
number = {10},
pages = {3940--3953},
year = {2022},
url = {https://doi.org/10.1109/TCSI.2022.3185135},
doi = {10.1109/TCSI.2022.3185135},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcasI/YueWQLWY22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcasI/WangQLWY22,
author = {Yang Wang and
Yubin Qin and
Leibo Liu and
Shaojun Wei and
Shouyi Yin},
title = {{SWPU:} {A} 126.04 {TFLOPS/W} Edge-Device Sparse {DNN} Training Processor
With Dynamic Sub-Structured Weight Pruning},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {69},
number = {10},
pages = {4014--4027},
year = {2022},
url = {https://doi.org/10.1109/TCSI.2022.3184175},
doi = {10.1109/TCSI.2022.3184175},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcasI/WangQLWY22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcasI/WangDLWY22,
author = {Yang Wang and
Dazheng Deng and
Leibo Liu and
Shaojun Wei and
Shouyi Yin},
title = {{PL-NPU:} An Energy-Efficient Edge-Device {DNN} Training Processor
With Posit-Based Logarithm-Domain Computing},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {69},
number = {10},
pages = {4042--4055},
year = {2022},
url = {https://doi.org/10.1109/TCSI.2022.3184115},
doi = {10.1109/TCSI.2022.3184115},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcasI/WangDLWY22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcasI/YangTLWLWY22,
author = {Jianxun Yang and
Fengbin Tu and
Yixuan Li and
Yiqi Wang and
Leibo Liu and
Shaojun Wei and
Shouyi Yin},
title = {{GQNA:} Generic Quantized {DNN} Accelerator With Weight-Repetition-Aware
Activation Aggregating},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {69},
number = {10},
pages = {4069--4082},
year = {2022},
url = {https://doi.org/10.1109/TCSI.2022.3188899},
doi = {10.1109/TCSI.2022.3188899},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcasI/YangTLWLWY22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tches/ChenYYWL22,
author = {Xiangren Chen and
Bohan Yang and
Shouyi Yin and
Shaojun Wei and
Leibo Liu},
title = {{CFNTT:} Scalable Radix-2/4 {NTT} Multiplication Architecture with
an Efficient Conflict-free Memory Mapping Scheme},
journal = {{IACR} Trans. Cryptogr. Hardw. Embed. Syst.},
volume = {2022},
number = {1},
pages = {94--126},
year = {2022},
url = {https://doi.org/10.46586/tches.v2022.i1.94-126},
doi = {10.46586/TCHES.V2022.I1.94-126},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tches/ChenYYWL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tches/ZhaoZWYZLZYWL22,
author = {Cankun Zhao and
Neng Zhang and
Hanning Wang and
Bohan Yang and
Wenping Zhu and
Zhengdong Li and
Min Zhu and
Shouyi Yin and
Shaojun Wei and
Leibo Liu},
title = {A Compact and High-Performance Hardware Architecture for CRYSTALS-Dilithium},
journal = {{IACR} Trans. Cryptogr. Hardw. Embed. Syst.},
volume = {2022},
number = {1},
pages = {270--295},
year = {2022},
url = {https://doi.org/10.46586/tches.v2022.i1.270-295},
doi = {10.46586/TCHES.V2022.I1.270-295},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tches/ZhaoZWYZLZYWL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/Chen0LYWL22,
author = {Xiangren Chen and
Bohan Yang and
Yong Lu and
Shouyi Yin and
Shaojun Wei and
Leibo Liu},
editor = {Rob Oshana},
title = {Efficient access scheme for multi-bank based {NTT} architecture through
conflict graph},
booktitle = {{DAC} '22: 59th {ACM/IEEE} Design Automation Conference, San Francisco,
California, USA, July 10 - 14, 2022},
pages = {91--96},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3489517.3530656},
doi = {10.1145/3489517.3530656},
timestamp = {Thu, 25 Aug 2022 14:23:32 +0200},
biburl = {https://dblp.org/rec/conf/dac/Chen0LYWL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/DengZWLDTGHXLWY22,
author = {Jinyi Deng and
Linyun Zhang and
Lei Wang and
Jiawei Liu and
Kexiang Deng and
Shibin Tang and
Jiangyuan Gu and
Boxiao Han and
Fei Xu and
Leibo Liu and
Shaojun Wei and
Shouyi Yin},
editor = {Rob Oshana},
title = {Mixed-granularity parallel coarse-grained reconfigurable architecture},
booktitle = {{DAC} '22: 59th {ACM/IEEE} Design Automation Conference, San Francisco,
California, USA, July 10 - 14, 2022},
pages = {343--348},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3489517.3530454},
doi = {10.1145/3489517.3530454},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/DengZWLDTGHXLWY22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/YueWLWY22,
author = {Zhiheng Yue and
Yabing Wang and
Leibo Liu and
Shaojun Wei and
Shouyi Yin},
editor = {Rob Oshana},
title = {{MC-CIM:} a reconfigurable computation-in-memory for efficient stereo
matching cost computation},
booktitle = {{DAC} '22: 59th {ACM/IEEE} Design Automation Conference, San Francisco,
California, USA, July 10 - 14, 2022},
pages = {457--462},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3489517.3530477},
doi = {10.1145/3489517.3530477},
timestamp = {Thu, 25 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/YueWLWY22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/ZhengZLWY22,
author = {Shixuan Zheng and
Xianjue Zhang and
Leibo Liu and
Shaojun Wei and
Shouyi Yin},
title = {Atomic Dataflow based Graph-Level Workload Orchestration for Scalable
{DNN} Accelerators},
booktitle = {{IEEE} International Symposium on High-Performance Computer Architecture,
{HPCA} 2022, Seoul, South Korea, April 2-6, 2022},
pages = {475--489},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/HPCA53966.2022.00042},
doi = {10.1109/HPCA53966.2022.00042},
timestamp = {Mon, 23 May 2022 16:36:22 +0200},
biburl = {https://dblp.org/rec/conf/hpca/ZhengZLWY22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/WuWWHZJYWL22,
author = {Yibo Wu and
Liang Wang and
Xiaohang Wang and
Jie Han and
Jianfeng Zhu and
Honglan Jiang and
Shouyi Yin and
Shaojun Wei and
Leibo Liu},
title = {Upward Packet Popup for Deadlock Freedom in Modular Chiplet-Based
Systems},
booktitle = {{IEEE} International Symposium on High-Performance Computer Architecture,
{HPCA} 2022, Seoul, South Korea, April 2-6, 2022},
pages = {986--1000},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/HPCA53966.2022.00076},
doi = {10.1109/HPCA53966.2022.00076},
timestamp = {Mon, 24 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hpca/WuWWHZJYWL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/YangZYWYWL22,
author = {Mingyuan Yang and
Yemeng Zhang and
Bohan Yang and
Hanning Wang and
Shouyi Yin and
Shaojun Wei and
Leibo Liu},
title = {A {SHA-512} Hardware Implementation Based on Block {RAM} Storage Structure},
booktitle = {{IEEE} International Parallel and Distributed Processing Symposium,
{IPDPS} Workshops 2022, Lyon, France, May 30 - June 3, 2022},
pages = {132--135},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/IPDPSW55747.2022.00031},
doi = {10.1109/IPDPSW55747.2022.00031},
timestamp = {Mon, 08 Aug 2022 16:44:20 +0200},
biburl = {https://dblp.org/rec/conf/ipps/YangZYWYWL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/Man0SYWL22,
author = {Xingchen Man and
Jianfeng Zhu and
Guihuan Song and
Shouyi Yin and
Shaojun Wei and
Leibo Liu},
editor = {Valentina Salapura and
Mohamed Zahran and
Fred Chong and
Lingjia Tang},
title = {CaSMap: agile mapper for reconfigurable spatial architectures by automatically
clustering intermediate representations and scattering mapping process},
booktitle = {{ISCA} '22: The 49th Annual International Symposium on Computer Architecture,
New York, New York, USA, June 18 - 22, 2022},
pages = {259--273},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3470496.3527426},
doi = {10.1145/3470496.3527426},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isca/Man0SYWL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/Tu0WLDKLWXY22,
author = {Fengbin Tu and
Yiqi Wang and
Zihan Wu and
Ling Liang and
Yufei Ding and
Bongjin Kim and
Leibo Liu and
Shaojun Wei and
Yuan Xie and
Shouyi Yin},
title = {A 28nm 29.2TFLOPS/W {BF16} and 36.5TOPS/W {INT8} Reconfigurable Digital
{CIM} Processor with Unified {FP/INT} Pipeline and Bitwise In-Memory
Booth Multiplication for Cloud Deep Learning Acceleration},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2022,
San Francisco, CA, USA, February 20-26, 2022},
pages = {1--3},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISSCC42614.2022.9731762},
doi = {10.1109/ISSCC42614.2022.9731762},
timestamp = {Wed, 25 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/Tu0WLDKLWXY22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/WangQDWZFCSLWY22,
author = {Yang Wang and
Yubin Qin and
Dazheng Deng and
Jingchuan Wei and
Yang Zhou and
Yuanqi Fan and
Tianbao Chen and
Hao Sun and
Leibo Liu and
Shaojun Wei and
Shouyi Yin},
title = {A 28nm 27.5TOPS/W Approximate-Computing-Based Transformer Processor
with Asymptotic Sparsity Speculating and Out-of-Order Computing},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2022,
San Francisco, CA, USA, February 20-26, 2022},
pages = {1--3},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISSCC42614.2022.9731686},
doi = {10.1109/ISSCC42614.2022.9731686},
timestamp = {Wed, 10 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/WangQDWZFCSLWY22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/TuWWLLDLWXY22,
author = {Fengbin Tu and
Zihan Wu and
Yiqi Wang and
Ling Liang and
Liu Liu and
Yufei Ding and
Leibo Liu and
Shaojun Wei and
Yuan Xie and
Shouyi Yin},
title = {A 28nm 15.59{\(\mathrm{\mu}\)}J/Token Full-Digital Bitline-Transpose
CIM-Based Sparse Transformer Accelerator with Pipeline/Parallel Reconfigurable
Modes},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2022,
San Francisco, CA, USA, February 20-26, 2022},
pages = {466--468},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISSCC42614.2022.9731645},
doi = {10.1109/ISSCC42614.2022.9731645},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/TuWWLLDLWXY22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ZhuZZLDCYYWL22,
author = {Yihong Zhu and
Wenping Zhu and
Min Zhu and
Chongyang Li and
Chenchen Deng and
Chen Chen and
Shuying Yin and
Shouyi Yin and
Shaojun Wei and
Leibo Liu},
title = {A 28nm 48KOPS 3.4{\(\mathrm{\mu}\)}J/Op Agile Crypto-Processor for
Post-Quantum Cryptography on Multi-Mathematical Problems},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2022,
San Francisco, CA, USA, February 20-26, 2022},
pages = {514--516},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISSCC42614.2022.9731783},
doi = {10.1109/ISSCC42614.2022.9731783},
timestamp = {Wed, 06 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/ZhuZZLDCYYWL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2210-08450,
author = {Hongjiang Chen and
Yang Wang and
Leibo Liu and
Shaojun Wei and
Shouyi Yin},
title = {{FAQS:} Communication-efficient Federate {DNN} Architecture and Quantization
Co-Search for personalized Hardware-aware Preferences},
journal = {CoRR},
volume = {abs/2210.08450},
year = {2022},
url = {https://doi.org/10.48550/arXiv.2210.08450},
doi = {10.48550/ARXIV.2210.08450},
eprinttype = {arXiv},
eprint = {2210.08450},
timestamp = {Wed, 19 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2210-08450.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2210-08485,
author = {Hongjiang Chen and
Yang Wang and
Leibo Liu and
Shaojun Wei and
Shouyi Yin},
title = {{HQNAS:} Auto {CNN} deployment framework for joint quantization and
architecture search},
journal = {CoRR},
volume = {abs/2210.08485},
year = {2022},
url = {https://doi.org/10.48550/arXiv.2210.08485},
doi = {10.48550/ARXIV.2210.08485},
eprinttype = {arXiv},
eprint = {2210.08485},
timestamp = {Wed, 19 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2210-08485.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/chinaf/HuangLZYW21,
author = {Hai Huang and
Leibo Liu and
Min Zhu and
Shouyi Yin and
Shaojun Wei},
title = {Fast substitution-box evaluation algorithm and its efficient masking
scheme for block ciphers},
journal = {Sci. China Inf. Sci.},
volume = {64},
number = {8},
year = {2021},
url = {https://doi.org/10.1007/s11432-020-3089-9},
doi = {10.1007/S11432-020-3089-9},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/chinaf/HuangLZYW21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/TuWWCXSLDCLWXY21,
author = {Fengbin Tu and
Weiwei Wu and
Yang Wang and
Hongjiang Chen and
Feng Xiong and
Man Shi and
Ning Li and
Jinyi Deng and
Tianbao Chen and
Leibo Liu and
Shaojun Wei and
Yuan Xie and
Shouyi Yin},
title = {Evolver: {A} Deep Learning Processor With On-Device Quantization-Voltage-Frequency
Tuning},
journal = {{IEEE} J. Solid State Circuits},
volume = {56},
number = {2},
pages = {658--673},
year = {2021},
url = {https://doi.org/10.1109/JSSC.2020.3021661},
doi = {10.1109/JSSC.2020.3021661},
timestamp = {Tue, 09 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/TuWWCXSLDCLWXY21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ZhuLLZWSLPDYWL21,
author = {Jianfeng Zhu and
Ao Luo and
Guanhua Li and
Bowei Zhang and
Yong Wang and
Gang Shan and
Yi Li and
Jianfeng Pan and
Chenchen Deng and
Shouyi Yin and
Shaojun Wei and
Leibo Liu},
title = {Jintide: Utilizing Low-Cost Reconfigurable External Monitors to Substantially
Enhance Hardware Security of Large-Scale {CPU} Clusters},
journal = {{IEEE} J. Solid State Circuits},
volume = {56},
number = {8},
pages = {2585--2601},
year = {2021},
url = {https://doi.org/10.1109/JSSC.2021.3058551},
doi = {10.1109/JSSC.2021.3058551},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/ZhuLLZWSLPDYWL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/TuWWCXSLDCLWXY21a,
author = {Fengbin Tu and
Weiwei Wu and
Yang Wang and
Hongjiang Chen and
Feng Xiong and
Man Shi and
Ning Li and
Jinyi Deng and
Tianbao Chen and
Leibo Liu and
Shaojun Wei and
Yuan Xie and
Shouyi Yin},
title = {Erratum to "Evolver: a Deep Learning Processor With On-Device
Quantization-Voltage-Frequency Tuning"},
journal = {{IEEE} J. Solid State Circuits},
volume = {56},
number = {9},
pages = {2895},
year = {2021},
url = {https://doi.org/10.1109/JSSC.2021.3058024},
doi = {10.1109/JSSC.2021.3058024},
timestamp = {Tue, 09 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/TuWWCXSLDCLWXY21a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/YangKZLZWLGHLLZ21,
author = {Jianxun Yang and
Yuyao Kong and
Zhao Zhang and
Zhuangzhi Liu and
Jing Zhou and
Yiqi Wang and
Yonggang Liu and
Chenfu Guo and
Te Hu and
Congcong Li and
Leibo Liu and
Jin Zhang and
Shaojun Wei and
Jun Yang and
Shouyi Yin},
title = {{TIMAQ:} {A} Time-Domain Computing-in-Memory-Based Processor Using
Predictable Decomposed Convolution for Arbitrary Quantized DNNs},
journal = {{IEEE} J. Solid State Circuits},
volume = {56},
number = {10},
pages = {3021--3038},
year = {2021},
url = {https://doi.org/10.1109/JSSC.2021.3095232},
doi = {10.1109/JSSC.2021.3095232},
timestamp = {Tue, 05 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/YangKZLZWLGHLLZ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhangQHYYWL21,
author = {Neng Zhang and
Qiao Qin and
Zongsheng Hou and
Bohan Yang and
Shouyi Yin and
Shaojun Wei and
Leibo Liu},
title = {Efficient Comparison and Addition for {FHE} With Weighted Computational
Complexity Model},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {40},
number = {9},
pages = {1896--1908},
year = {2021},
url = {https://doi.org/10.1109/TCAD.2020.3031266},
doi = {10.1109/TCAD.2020.3031266},
timestamp = {Mon, 05 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ZhangQHYYWL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WuWWHYWL21,
author = {Yibo Wu and
Liang Wang and
Xiaohang Wang and
Jie Han and
Shouyi Yin and
Shaojun Wei and
Leibo Liu},
title = {A Deflection-Based Deadlock Recovery Framework to Achieve High Throughput
for Faulty NoCs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {40},
number = {10},
pages = {2170--2183},
year = {2021},
url = {https://doi.org/10.1109/TCAD.2020.3037310},
doi = {10.1109/TCAD.2020.3037310},
timestamp = {Mon, 24 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WuWWHYWL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tim/ZhouYOLT21,
author = {Kai Zhou and
Shouyi Yin and
Peng Ouyang and
Yinan Liu and
Shibin Tang},
title = {Flexible Rectification of a Speckle Projection System for Depth Sensing},
journal = {{IEEE} Trans. Instrum. Meas.},
volume = {70},
pages = {1--13},
year = {2021},
url = {https://doi.org/10.1109/TIM.2021.3085950},
doi = {10.1109/TIM.2021.3085950},
timestamp = {Tue, 13 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tim/ZhouYOLT21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tmm/MoLZLYW21,
author = {Huiyu Mo and
Leibo Liu and
Wenping Zhu and
Qiang Li and
Shouyi Yin and
Shaojun Wei},
title = {A 460 {GOPS/W} Improved Mnemonic Descent Method-Based Hardwired Accelerator
for Face Alignment},
journal = {{IEEE} Trans. Multim.},
volume = {23},
pages = {1122--1135},
year = {2021},
url = {https://doi.org/10.1109/TMM.2020.2993943},
doi = {10.1109/TMM.2020.2993943},
timestamp = {Wed, 07 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tmm/MoLZLYW21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tpds/ChenZDLCJYWL21,
author = {Longlong Chen and
Jianfeng Zhu and
Yangdong Deng and
Zhaoshi Li and
Jian Chen and
Xiaowei Jiang and
Shouyi Yin and
Shaojun Wei and
Leibo Liu},
title = {An Elastic Task Scheduling Scheme on Coarse-Grained Reconfigurable
Architectures},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {32},
number = {12},
pages = {3066--3080},
year = {2021},
url = {https://doi.org/10.1109/TPDS.2021.3084804},
doi = {10.1109/TPDS.2021.3084804},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tpds/ChenZDLCJYWL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aicas/WangDLWY21,
author = {Yang Wang and
Dazheng Deng and
Leibo Liu and
Shaojun Wei and
Shouyi Yin},
title = {{LPE:} Logarithm Posit Processing Element for Energy-Efficient Edge-Device
Training},
booktitle = {3rd {IEEE} International Conference on Artificial Intelligence Circuits
and Systems, {AICAS} 2021, Washington, DC, USA, June 6-9, 2021},
pages = {1--4},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/AICAS51828.2021.9458421},
doi = {10.1109/AICAS51828.2021.9458421},
timestamp = {Wed, 10 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aicas/WangDLWY21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aicas/WangQLWY21,
author = {Yang Wang and
Yubin Qin and
Leibo Liu and
Shaojun Wei and
Shouyi Yin},
title = {{HPPU:} An Energy-Efficient Sparse {DNN} Training Processor with Hybrid
Weight Pruning},
booktitle = {3rd {IEEE} International Conference on Artificial Intelligence Circuits
and Systems, {AICAS} 2021, Washington, DC, USA, June 6-9, 2021},
pages = {1--4},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/AICAS51828.2021.9458410},
doi = {10.1109/AICAS51828.2021.9458410},
timestamp = {Wed, 10 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aicas/WangQLWY21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/LiGYLW21,
author = {Cheng Li and
Jiangyuan Gu and
Shouyi Yin and
Leibo Liu and
Shaojun Wei},
title = {Combining Memory Partitioning and Subtask Generation for Parallel
Data Access on CGRAs},
booktitle = {{ASPDAC} '21: 26th Asia and South Pacific Design Automation Conference,
Tokyo, Japan, January 18-21, 2021},
pages = {204--209},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3394885.3431414},
doi = {10.1145/3394885.3431414},
timestamp = {Mon, 03 May 2021 16:42:27 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/LiGYLW21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ZhangGYLW21,
author = {Song Zhang and
Jiangyuan Gu and
Shouyi Yin and
Leibo Liu and
Shaojun Wei},
title = {A Multiple-Precision Multiply and Accumulation Design with Multiply-Add
Merged Strategy for {AI} Accelerating},
booktitle = {{ASPDAC} '21: 26th Asia and South Pacific Design Automation Conference,
Tokyo, Japan, January 18-21, 2021},
pages = {229--234},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3394885.3431531},
doi = {10.1145/3394885.3431531},
timestamp = {Tue, 09 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/ZhangGYLW21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asru/ShiCKYO21,
author = {Huiyu Shi and
Xi Chen and
Tianlong Kong and
Shouyi Yin and
Peng Ouyang},
title = {GLMSnet: Single Channel Speech Separation Framework in Noisy and Reverberant
Environments},
booktitle = {{IEEE} Automatic Speech Recognition and Understanding Workshop, {ASRU}
2021, Cartagena, Colombia, December 13-17, 2021},
pages = {663--670},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ASRU51503.2021.9688217},
doi = {10.1109/ASRU51503.2021.9688217},
timestamp = {Wed, 09 Feb 2022 09:03:03 +0100},
biburl = {https://dblp.org/rec/conf/asru/ShiCKYO21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/WangWJTYH21,
author = {Zhendong Wang and
Rujia Wang and
Zihang Jiang and
Xulong Tang and
Shouyi Yin and
Yang Hu},
title = {Towards a Secure Integrated Heterogeneous Platform via Cooperative
{CPU/GPU} Encryption},
booktitle = {30th {IEEE} Asian Test Symposium, {ATS} 2021, Matsuyama, Ehime, Japan,
November 22-25, 2021},
pages = {115--120},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ATS52891.2021.00032},
doi = {10.1109/ATS52891.2021.00032},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ats/WangWJTYH21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/LinSTLLWY21,
author = {Xinhan Lin and
Liang Sun and
Fengbin Tu and
Leibo Liu and
Xiangyu Li and
Shaojun Wei and
Shouyi Yin},
title = {{ADROIT:} An Adaptive Dynamic Refresh Optimization Framework for {DRAM}
Energy Saving In {DNN} Training},
booktitle = {58th {ACM/IEEE} Design Automation Conference, {DAC} 2021, San Francisco,
CA, USA, December 5-9, 2021},
pages = {751--756},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/DAC18074.2021.9586265},
doi = {10.1109/DAC18074.2021.9586265},
timestamp = {Fri, 12 Nov 2021 12:31:50 +0100},
biburl = {https://dblp.org/rec/conf/dac/LinSTLLWY21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/YangLWYWL21,
author = {Haichang Yang and
Zhaoshi Li and
Jiawei Wang and
Shouyi Yin and
Shaojun Wei and
Leibo Liu},
title = {HeteroKV: {A} Scalable Line-rate Key-Value Store on Heterogeneous
{CPU-FPGA} Platforms},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2021, Grenoble, France, February 1-5, 2021},
pages = {834--837},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.23919/DATE51398.2021.9474088},
doi = {10.23919/DATE51398.2021.9474088},
timestamp = {Wed, 21 Jul 2021 10:04:34 +0200},
biburl = {https://dblp.org/rec/conf/date/YangLWYWL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/YangZLZLWY21,
author = {Jianxun Yang and
Zhao Zhang and
Zhuangzhi Liu and
Jing Zhou and
Leibo Liu and
Shaojun Wei and
Shouyi Yin},
title = {FuseKNA: Fused Kernel Convolution based Accelerator for Deep Neural
Networks},
booktitle = {{IEEE} International Symposium on High-Performance Computer Architecture,
{HPCA} 2021, Seoul, South Korea, February 27 - March 3, 2021},
pages = {894--907},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/HPCA51647.2021.00079},
doi = {10.1109/HPCA51647.2021.00079},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hpca/YangZLZLWY21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/LiuLMSY21,
author = {Dajiang Liu and
Ting Liu and
Xingyu Mo and
Jiaxing Shang and
Shouyi Yin},
title = {Polyhedral-based Pipelining of Imperfectly-Nested Loop for CGRAs},
booktitle = {{IEEE/ACM} International Conference On Computer Aided Design, {ICCAD}
2021, Munich, Germany, November 1-4, 2021},
pages = {1--9},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ICCAD51958.2021.9643542},
doi = {10.1109/ICCAD51958.2021.9643542},
timestamp = {Tue, 28 Dec 2021 12:29:05 +0100},
biburl = {https://dblp.org/rec/conf/iccad/LiuLMSY21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iconac/SunCWWY21,
author = {Hao Sun and
Yujuan Cheng and
Yang Wang and
Bin Wang and
Shouyi Yin},
title = {Learnable Quantization Loss Function Based on Expectation},
booktitle = {26th International Conference on Automation and Computing, {ICAC}
2021, Portsmouth, United Kingdom, September 2-4, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.23919/ICAC50006.2021.9594164},
doi = {10.23919/ICAC50006.2021.9594164},
timestamp = {Wed, 10 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iconac/SunCWWY21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/interspeech/KongYZGWSHSW21,
author = {Tianlong Kong and
Shouyi Yin and
Dawei Zhang and
Wang Geng and
Xin Wang and
Dandan Song and
Jinwen Huang and
Huiyu Shi and
Xiaorui Wang},
editor = {Hynek Hermansky and
Honza Cernock{\'{y}} and
Luk{\'{a}}s Burget and
Lori Lamel and
Odette Scharenborg and
Petr Motl{\'{\i}}cek},
title = {Dynamic Multi-Scale Convolution for Dialect Identification},
booktitle = {Interspeech 2021, 22nd Annual Conference of the International Speech
Communication Association, Brno, Czechia, 30 August - 3 September
2021},
pages = {3261--3265},
publisher = {{ISCA}},
year = {2021},
url = {https://doi.org/10.21437/Interspeech.2021-56},
doi = {10.21437/INTERSPEECH.2021-56},
timestamp = {Wed, 21 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/interspeech/KongYZGWSHSW21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/SunLYWL21,
author = {Weiyi Sun and
Zhaoshi Li and
Shouyi Yin and
Shaojun Wei and
Leibo Liu},
title = {{ABC-DIMM:} Alleviating the Bottleneck of Communication in DIMM-based
Near-Memory Processing with Inter-DIMM Broadcast},
booktitle = {48th {ACM/IEEE} Annual International Symposium on Computer Architecture,
{ISCA} 2021, Virtual Event / Valencia, Spain, June 14-18, 2021},
pages = {237--250},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISCA52012.2021.00027},
doi = {10.1109/ISCA52012.2021.00027},
timestamp = {Mon, 19 Feb 2024 07:32:07 +0100},
biburl = {https://dblp.org/rec/conf/isca/SunLYWL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/MoZHWLLYWL21,
author = {Huiyu Mo and
Wenping Zhu and
Wenjing Hu and
Guangbin Wang and
Qiang Li and
Ang Li and
Shouyi Yin and
Shaojun Wei and
Leibo Liu},
title = {9.2A 28nm 12.1TOPS/W Dual-Mode {CNN} Processor Using Effective-Weight-Based
Convolution and Error-Compensation-Based Prediction},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2021,
San Francisco, CA, USA, February 13-22, 2021},
pages = {146--148},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISSCC42613.2021.9365943},
doi = {10.1109/ISSCC42613.2021.9365943},
timestamp = {Wed, 10 Mar 2021 15:02:58 +0100},
biburl = {https://dblp.org/rec/conf/isscc/MoZHWLLYWL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/GuoYSHLTWLCLWY21,
author = {Ruiqi Guo and
Zhiheng Yue and
Xin Si and
Te Hu and
Hao Li and
Limei Tang and
Yabing Wang and
Leibo Liu and
Meng{-}Fan Chang and
Qiang Li and
Shaojun Wei and
Shouyi Yin},
title = {15.4 {A} 5.99-to-691.1TOPS/W Tensor-Train In-Memory-Computing Processor
Using Bit-Level-Sparsity-Based Optimization and Variable-Precision
Quantization},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2021,
San Francisco, CA, USA, February 13-22, 2021},
pages = {242--244},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISSCC42613.2021.9365989},
doi = {10.1109/ISSCC42613.2021.9365989},
timestamp = {Wed, 25 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/GuoYSHLTWLCLWY21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/GuoLLZTSLCWY21,
author = {Ruiqi Guo and
Hao Li and
Ruhui Liu and
Zhixiao Zhang and
Limei Tang and
Hao Sun and
Leibo Liu and
Meng{-}Fan Chang and
Shaojun Wei and
Shouyi Yin},
title = {A 6.54-to-26.03 {TOPS/W} Computing-In-Memory {RNN} Processor using
Input Similarity Optimization and Attention-based Context-breaking
with Output Speculation},
booktitle = {2021 Symposium on {VLSI} Circuits, Kyoto, Japan, June 13-19, 2021},
pages = {1--2},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.23919/VLSICircuits52068.2021.9492492},
doi = {10.23919/VLSICIRCUITS52068.2021.9492492},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/GuoLLZTSLCWY21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/WangQDWCLLWY21,
author = {Yang Wang and
Yubin Qin and
Dazheng Deng and
Jingchuan Wei and
Tianbao Chen and
Xinhan Lin and
Leibo Liu and
Shaojun Wei and
Shouyi Yin},
title = {A 28nm 276.55TFLOPS/W Sparse Deep-Neural-Network Training Processor
with Implicit Redundancy Speculation and Batch Normalization Reformulation},
booktitle = {2021 Symposium on {VLSI} Circuits, Kyoto, Japan, June 13-19, 2021},
pages = {1--2},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.23919/VLSICircuits52068.2021.9492420},
doi = {10.23919/VLSICIRCUITS52068.2021.9492420},
timestamp = {Wed, 10 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/WangQDWCLLWY21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2108-07787,
author = {Tianlong Kong and
Shouyi Yin and
Dawei Zhang and
Wang Geng and
Xin Wang and
Dandan Song and
Jinwen Huang and
Huiyu Shi and
Xiaorui Wang},
title = {Dynamic Multi-scale Convolution for Dialect Identification},
journal = {CoRR},
volume = {abs/2108.07787},
year = {2021},
url = {https://arxiv.org/abs/2108.07787},
eprinttype = {arXiv},
eprint = {2108.07787},
timestamp = {Fri, 20 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2108-07787.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/csur/LiuZLLDHYW20,
author = {Leibo Liu and
Jianfeng Zhu and
Zhaoshi Li and
Yanan Lu and
Yangdong Deng and
Jie Han and
Shouyi Yin and
Shaojun Wei},
title = {A Survey of Coarse-Grained Reconfigurable Architecture and Design:
Taxonomy, Challenges, and Applications},
journal = {{ACM} Comput. Surv.},
volume = {52},
number = {6},
pages = {118:1--118:39},
year = {2020},
url = {https://doi.org/10.1145/3357375},
doi = {10.1145/3357375},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/csur/LiuZLLDHYW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/PengLZYW20,
author = {Guiqiang Peng and
Leibo Liu and
Sheng Zhou and
Shouyi Yin and
Shaojun Wei},
title = {A 2.92-Gb/s/W and 0.43-Gb/s/MG Flexible and Scalable CGRA-Based Baseband
Processor for Massive {MIMO} Detection},
journal = {{IEEE} J. Solid State Circuits},
volume = {55},
number = {2},
pages = {505--519},
year = {2020},
url = {https://doi.org/10.1109/JSSC.2019.2952839},
doi = {10.1109/JSSC.2019.2952839},
timestamp = {Wed, 22 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/PengLZYW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/ZhangQYZYWL20,
author = {Neng Zhang and
Qiao Qin and
Hang Yuan and
Chenggao Zhou and
Shouyi Yin and
Shaojun Wei and
Leibo Liu},
title = {{NTTU:} An Area-Efficient Low-Power NTT-Uncoupled Architecture for
NTT-Based Multiplication},
journal = {{IEEE} Trans. Computers},
volume = {69},
number = {4},
pages = {520--533},
year = {2020},
url = {https://doi.org/10.1109/TC.2019.2958334},
doi = {10.1109/TC.2019.2958334},
timestamp = {Mon, 05 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tc/ZhangQYZYWL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhengZOTLWY20,
author = {Shixuan Zheng and
Xianjue Zhang and
Daoli Ou and
Shibin Tang and
Leibo Liu and
Shaojun Wei and
Shouyi Yin},
title = {Efficient Scheduling of Irregular Network Structures on {CNN} Accelerators},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {39},
number = {11},
pages = {3408--3419},
year = {2020},
url = {https://doi.org/10.1109/TCAD.2020.3012215},
doi = {10.1109/TCAD.2020.3012215},
timestamp = {Thu, 17 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ZhengZOTLWY20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangJWTLYH20,
author = {Zhendong Wang and
Zihang Jiang and
Zhen Wang and
Xulong Tang and
Cong Liu and
Shouyi Yin and
Yang Hu},
title = {Enabling Latency-Aware Data Initialization for Integrated {CPU/GPU}
Heterogeneous Platform},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {39},
number = {11},
pages = {3433--3444},
year = {2020},
url = {https://doi.org/10.1109/TCAD.2020.3013047},
doi = {10.1109/TCAD.2020.3013047},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangJWTLYH20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/DengWLZWLYW20,
author = {Chenchen Deng and
Bo Wang and
Leibo Liu and
Min Zhu and
Youyu Wu and
Hui Li and
Shouyi Yin and
Shaojun Wei},
title = {A 60 Gb/s-Level Coarse-Grained Reconfigurable Cryptographic Processor
With Less Than 1-W Power},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {67-II},
number = {2},
pages = {375--379},
year = {2020},
url = {https://doi.org/10.1109/TCSII.2019.2909046},
doi = {10.1109/TCSII.2019.2909046},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/DengWLZWLYW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/WangLHYYWZZWLCR20,
author = {Hang Wang and
Xiang Li and
Daqiang Han and
Shiquan Yu and
Shouyi Yin and
Shaojun Wei and
Nanning Zheng and
Xuchong Zhang and
Tiancheng Wang and
Wenchang Li and
Qiubo Chen and
Pengju Ren and
Xiaogang Wu and
Hongbin Sun and
Zhiqiang Jiang},
title = {A 4K {\texttimes} 2K@60fps Multifunctional Video Display Processor
for High Perceptual Image Quality},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {67-I},
number = {2},
pages = {451--463},
year = {2020},
url = {https://doi.org/10.1109/TCSI.2019.2921943},
doi = {10.1109/TCSI.2019.2921943},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/WangLHYYWZZWLCR20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tches/ZhangYCYWL20,
author = {Neng Zhang and
Bohan Yang and
Chen Chen and
Shouyi Yin and
Shaojun Wei and
Leibo Liu},
title = {Highly Efficient Architecture of NewHope-NIST on {FPGA} using Low-Complexity
{NTT/INTT}},
journal = {{IACR} Trans. Cryptogr. Hardw. Embed. Syst.},
volume = {2020},
number = {2},
pages = {49--72},
year = {2020},
url = {https://doi.org/10.13154/tches.v2020.i2.49-72},
doi = {10.13154/TCHES.V2020.I2.49-72},
timestamp = {Wed, 06 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tches/ZhangYCYWL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcsv/MoLZLLYW20,
author = {Huiyu Mo and
Leibo Liu and
Wenping Zhu and
Qiang Li and
Hong Liu and
Shouyi Yin and
Shaojun Wei},
title = {A Multi-Task Hardwired Accelerator for Face Detection and Alignment},
journal = {{IEEE} Trans. Circuits Syst. Video Technol.},
volume = {30},
number = {11},
pages = {4284--4298},
year = {2020},
url = {https://doi.org/10.1109/TCSVT.2019.2955463},
doi = {10.1109/TCSVT.2019.2955463},
timestamp = {Thu, 17 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcsv/MoLZLLYW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tpds/WangLHWYW20,
author = {Liang Wang and
Leibo Liu and
Jie Han and
Xiaohang Wang and
Shouyi Yin and
Shaojun Wei},
title = {Achieving Flexible Global Reconfiguration in NoCs Using Reconfigurable
Rings},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {31},
number = {3},
pages = {611--622},
year = {2020},
url = {https://doi.org/10.1109/TPDS.2019.2940190},
doi = {10.1109/TPDS.2019.2940190},
timestamp = {Mon, 24 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tpds/WangLHWYW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tpds/LiuMZYW20,
author = {Leibo Liu and
Xingchen Man and
Jianfeng Zhu and
Shouyi Yin and
Shaojun Wei},
title = {Pattern-Based Dynamic Compilation System for CGRAs With Online Configuration
Transformation},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {31},
number = {12},
pages = {2981--2994},
year = {2020},
url = {https://doi.org/10.1109/TPDS.2020.3007492},
doi = {10.1109/TPDS.2020.3007492},
timestamp = {Fri, 02 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tpds/LiuMZYW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tsp/LiuPWZWYW20,
author = {Leibo Liu and
Guiqiang Peng and
Pan Wang and
Sheng Zhou and
Qiushi Wei and
Shouyi Yin and
Shaojun Wei},
title = {Energy- and Area-Efficient Recursive-Conjugate-Gradient-Based {MMSE}
Detector for Massive {MIMO} Systems},
journal = {{IEEE} Trans. Signal Process.},
volume = {68},
pages = {573--588},
year = {2020},
url = {https://doi.org/10.1109/TSP.2020.2964234},
doi = {10.1109/TSP.2020.2964234},
timestamp = {Wed, 22 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tsp/LiuPWZWYW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/twc/WangLZPYW20,
author = {Pan Wang and
Leibo Liu and
Sheng Zhou and
Guiqiang Peng and
Shouyi Yin and
Shaojun Wei},
title = {Near-Optimal {MIMO-SCMA} Uplink Detection With Low-Complexity Expectation
Propagation},
journal = {{IEEE} Trans. Wirel. Commun.},
volume = {19},
number = {2},
pages = {1025--1037},
year = {2020},
url = {https://doi.org/10.1109/TWC.2019.2950314},
doi = {10.1109/TWC.2019.2950314},
timestamp = {Wed, 22 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/twc/WangLZPYW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/YangKZLZWLGHLLZ20,
author = {Jianxun Yang and
Yuyao Kong and
Zhao Zhang and
Zhuangzhi Liu and
Jing Zhou and
Yiqi Wang and
Yonggang Liu and
Chenfu Guo and
Te Hu and
Congcong Li and
Leibo Liu and
Jin Zhang and
Shaojun Wei and
Jun Yang and
Shouyi Yin},
title = {A Time-Domain Computing-in-Memory based Processor using Predictable
Decomposed Convolution for Arbitrary Quantized DNNs},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2020, Virtual
Event, Japan, November 9-11, 2020},
pages = {1--4},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/A-SSCC48613.2020.9336145},
doi = {10.1109/A-SSCC48613.2020.9336145},
timestamp = {Thu, 22 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asscc/YangKZLZWLGHLLZ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/KouGWYY20,
author = {Mingyang Kou and
Jiangyuan Gu and
Shaojun Wei and
Hailong Yao and
Shouyi Yin},
title = {{TAEM:} Fast Transfer-Aware Effective Loop Mapping for Heterogeneous
Resources on {CGRA}},
booktitle = {57th {ACM/IEEE} Design Automation Conference, {DAC} 2020, San Francisco,
CA, USA, July 20-24, 2020},
pages = {1--6},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/DAC18072.2020.9218668},
doi = {10.1109/DAC18072.2020.9218668},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/KouGWYY20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/XiongTSWLWY20,
author = {Feng Xiong and
Fengbin Tu and
Man Shi and
Yang Wang and
Leibo Liu and
Shaojun Wei and
Shouyi Yin},
title = {{STC:} Significance-aware Transform-based Codec Framework for External
Memory Access Reduction},
booktitle = {57th {ACM/IEEE} Design Automation Conference, {DAC} 2020, San Francisco,
CA, USA, July 20-24, 2020},
pages = {1--6},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/DAC18072.2020.9218522},
doi = {10.1109/DAC18072.2020.9218522},
timestamp = {Wed, 10 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/XiongTSWLWY20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/LiLWY20,
author = {Ning Li and
Leibo Liu and
Shaojun Wei and
Shouyi Yin},
title = {A High-performance Inference Accelerator Exploiting Patterned Sparsity
in CNNs},
booktitle = {28th {IEEE} Annual International Symposium on Field-Programmable Custom
Computing Machines, {FCCM} 2020, Fayetteville, AR, USA, May 3-6, 2020},
pages = {243},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/FCCM48280.2020.00076},
doi = {10.1109/FCCM48280.2020.00076},
timestamp = {Thu, 25 Jun 2020 14:25:04 +0200},
biburl = {https://dblp.org/rec/conf/fccm/LiLWY20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icassp/LiJYSOLW20,
author = {Peishuo Li and
Zihang Jiang and
Shouyi Yin and
Dandan Song and
Peng Ouyang and
Leibo Liu and
Shaojun Wei},
title = {{PAGAN:} {A} Phase-Adapted Generative Adversarial Networks for Speech
Enhancement},
booktitle = {2020 {IEEE} International Conference on Acoustics, Speech and Signal
Processing, {ICASSP} 2020, Barcelona, Spain, May 4-8, 2020},
pages = {6234--6238},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ICASSP40776.2020.9054256},
doi = {10.1109/ICASSP40776.2020.9054256},
timestamp = {Thu, 23 Jul 2020 16:19:28 +0200},
biburl = {https://dblp.org/rec/conf/icassp/LiJYSOLW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icdsp2/LuLLYW20,
author = {Yanan Lu and
Leibo Liu and
Jian Liu and
Shouyi Yin and
Shaojun Wei},
title = {A Reconfigurable Branch Predictor for Spatial Computing Architectures},
booktitle = {{ICDSP} 2020: 4th International Conference on Digital Signal Processing,
Chengdu, China, June 19-21, 2020},
pages = {295--299},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3408127.3408168},
doi = {10.1145/3408127.3408168},
timestamp = {Thu, 18 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icdsp2/LuLLYW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/interspeech/ChenZSOY20,
author = {Xi Chen and
Songyang Zhang and
Dandan Song and
Peng Ouyang and
Shouyi Yin},
editor = {Helen Meng and
Bo Xu and
Thomas Fang Zheng},
title = {Transformer with Bidirectional Decoder for Speech Recognition},
booktitle = {Interspeech 2020, 21st Annual Conference of the International Speech
Communication Association, Virtual Event, Shanghai, China, 25-29 October
2020},
pages = {1773--1777},
publisher = {{ISCA}},
year = {2020},
url = {https://doi.org/10.21437/Interspeech.2020-2677},
doi = {10.21437/INTERSPEECH.2020-2677},
timestamp = {Fri, 29 Jan 2021 17:40:16 +0100},
biburl = {https://dblp.org/rec/conf/interspeech/ChenZSOY20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/interspeech/LiLSLWXOZC0YH20,
author = {Ruyun Li and
Tianyu Liang and
Dandan Song and
Yi Liu and
Yangcheng Wu and
Can Xu and
Peng Ouyang and
Xianwei Zhang and
Xianhong Chen and
Weiqiang Zhang and
Shouyi Yin and
Liang He},
editor = {Helen Meng and
Bo Xu and
Thomas Fang Zheng},
title = {{THUEE} System for {NIST} {SRE19} {CTS} Challenge},
booktitle = {Interspeech 2020, 21st Annual Conference of the International Speech
Communication Association, Virtual Event, Shanghai, China, 25-29 October
2020},
pages = {2232--2236},
publisher = {{ISCA}},
year = {2020},
url = {https://doi.org/10.21437/Interspeech.2020-1245},
doi = {10.21437/INTERSPEECH.2020-1245},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/interspeech/LiLSLWXOZC0YH20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/YangLDLYWL20,
author = {Yifan Yang and
Zhaoshi Li and
Yangdong Deng and
Zhiwei Liu and
Shouyi Yin and
Shaojun Wei and
Leibo Liu},
title = {GraphABCD: Scaling Out Graph Analytics with Asynchronous Block Coordinate
Descent},
booktitle = {47th {ACM/IEEE} Annual International Symposium on Computer Architecture,
{ISCA} 2020, Virtual Event / Valencia, Spain, May 30 - June 3, 2020},
pages = {419--432},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISCA45697.2020.00043},
doi = {10.1109/ISCA45697.2020.00043},
timestamp = {Mon, 19 Feb 2024 07:32:24 +0100},
biburl = {https://dblp.org/rec/conf/isca/YangLDLYWL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/ChenLXLYYWL20,
author = {Dibei Chen and
Zhaoshi Li and
Tianzhu Xiong and
Zhiwei Liu and
Jun Yang and
Shouyi Yin and
Shaojun Wei and
Leibo Liu},
title = {{CATCAM:} Constant-time Alteration Ternary {CAM} with Scalable In-Memory
Architecture},
booktitle = {53rd Annual {IEEE/ACM} International Symposium on Microarchitecture,
{MICRO} 2020, Athens, Greece, October 17-21, 2020},
pages = {342--355},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/MICRO50266.2020.00038},
doi = {10.1109/MICRO50266.2020.00038},
timestamp = {Sun, 30 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/micro/ChenLXLYYWL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/MoLHZLLYCJW20,
author = {Huiyu Mo and
Leibo Liu and
Wenjing Hu and
Wenping Zhu and
Qiang Li and
Ang Li and
Shouyi Yin and
Jian Chen and
Xiaowei Jiang and
Shaojun Wei},
title = {{TFE:} Energy-efficient Transferred Filter-based Engine to Compress
and Accelerate Convolutional Neural Networks},
booktitle = {53rd Annual {IEEE/ACM} International Symposium on Microarchitecture,
{MICRO} 2020, Athens, Greece, October 17-21, 2020},
pages = {751--765},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/MICRO50266.2020.00067},
doi = {10.1109/MICRO50266.2020.00067},
timestamp = {Tue, 17 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/micro/MoLHZLLYCJW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2008-04481,
author = {Xi Chen and
Songyang Zhang and
Dandan Song and
Peng Ouyang and
Shouyi Yin},
title = {Transformer with Bidirectional Decoder for Speech Recognition},
journal = {CoRR},
volume = {abs/2008.04481},
year = {2020},
url = {https://arxiv.org/abs/2008.04481},
eprinttype = {arXiv},
eprint = {2008.04481},
timestamp = {Mon, 17 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2008-04481.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/YinOYLLLW19,
author = {Shouyi Yin and
Peng Ouyang and
Jianxun Yang and
Tianyi Lu and
Xiudong Li and
Leibo Liu and
Shaojun Wei},
title = {An Energy-Efficient Reconfigurable Processor for Binary-and Ternary-Weight
Neural Networks With Flexible Data Bit Width},
journal = {{IEEE} J. Solid State Circuits},
volume = {54},
number = {4},
pages = {1120--1136},
year = {2019},
url = {https://doi.org/10.1109/JSSC.2018.2881913},
doi = {10.1109/JSSC.2018.2881913},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/YinOYLLLW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/ZhaoOKYZWZ19,
author = {Yinglin Zhao and
Peng Ouyang and
Wang Kang and
Shouyi Yin and
Youguang Zhang and
Shaojun Wei and
Weisheng Zhao},
title = {An {STT-MRAM} Based in Memory Architecture for Low Power Integral
Computing},
journal = {{IEEE} Trans. Computers},
volume = {68},
number = {4},
pages = {617--623},
year = {2019},
url = {https://doi.org/10.1109/TC.2018.2879502},
doi = {10.1109/TC.2018.2879502},
timestamp = {Mon, 02 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/ZhaoOKYZWZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuangLHCYW19,
author = {Hai Huang and
Leibo Liu and
Qihuan Huang and
Yingjie Chen and
Shouyi Yin and
Shaojun Wei},
title = {Low Area-Overhead Low-Entropy Masking Scheme {(LEMS)} Against Correlation
Power Analysis Attack},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {2},
pages = {208--219},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2802867},
doi = {10.1109/TCAD.2018.2802867},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuangLHCYW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YinTLOTLW19,
author = {Shouyi Yin and
Shibin Tang and
Xinhan Lin and
Peng Ouyang and
Fengbin Tu and
Leibo Liu and
Shaojun Wei},
title = {A High Throughput Acceleration for Hybrid Neural Networks With Efficient
Resource Management on {FPGA}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {4},
pages = {678--691},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2821561},
doi = {10.1109/TCAD.2018.2821561},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YinTLOTLW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuZYW19,
author = {Leibo Liu and
Wenping Zhu and
Shouyi Yin and
Shaojun Wei},
title = {A Binary-Feature-Based Object Recognition Accelerator With 22 M-Vector/s
Throughput and 0.68 G-Vector/J Energy-Efficiency for Full-HD Resolution},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {7},
pages = {1265--1277},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2846634},
doi = {10.1109/TCAD.2018.2846634},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuZYW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangLLHLWYWM19,
author = {Liang Wang and
Ping Lv and
Leibo Liu and
Jie Han and
Ho{-}fung Leung and
Xiaohang Wang and
Shouyi Yin and
Shaojun Wei and
Terrence S. T. Mak},
title = {A Lifetime Reliability-Constrained Runtime Mapping for Throughput
Optimization in Many-Core Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {9},
pages = {1771--1784},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2855168},
doi = {10.1109/TCAD.2018.2855168},
timestamp = {Mon, 24 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangLLHLWYWM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuYLSLWFZ19,
author = {Dajiang Liu and
Shouyi Yin and
Guojie Luo and
Jiaxing Shang and
Leibo Liu and
Shaojun Wei and
Yong Feng and
Shangbo Zhou},
title = {Data-Flow Graph Mapping Optimization for {CGRA} With Deep Reinforcement
Learning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {12},
pages = {2271--2283},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2878183},
doi = {10.1109/TCAD.2018.2878183},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuYLSLWFZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/ShiOYLW19,
author = {Man Shi and
Peng Ouyang and
Shouyi Yin and
Leibo Liu and
Shaojun Wei},
title = {A Fast and Power-Efficient Hardware Architecture for Non-Maximum Suppression},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {66-II},
number = {11},
pages = {1870--1874},
year = {2019},
url = {https://doi.org/10.1109/TCSII.2019.2893527},
doi = {10.1109/TCSII.2019.2893527},
timestamp = {Wed, 27 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/ShiOYLW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/ZhengOSLLWY19,
author = {Shixuan Zheng and
Peng Ouyang and
Dandan Song and
Xiudong Li and
Leibo Liu and
Shaojun Wei and
Shouyi Yin},
title = {An Ultra-Low Power Binarized Convolutional Neural Network-Based Speech
Recognition Processor With On-Chip Self-Learning},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {66-I},
number = {12},
pages = {4648--4661},
year = {2019},
url = {https://doi.org/10.1109/TCSI.2019.2942092},
doi = {10.1109/TCSI.2019.2942092},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/ZhengOSLLWY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcsv/TuYOLW19,
author = {Fengbin Tu and
Shouyi Yin and
Peng Ouyang and
Leibo Liu and
Shaojun Wei},
title = {Reconfigurable Architecture for Neural Approximation in Multimedia
Computing},
journal = {{IEEE} Trans. Circuits Syst. Video Technol.},
volume = {29},
number = {3},
pages = {892--906},
year = {2019},
url = {https://doi.org/10.1109/TCSVT.2018.2812781},
doi = {10.1109/TCSVT.2018.2812781},
timestamp = {Tue, 25 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcsv/TuYOLW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcsv/LiuWZMWYSW19,
author = {Leibo Liu and
Qiang Wang and
Wenping Zhu and
Huiyu Mo and
Tianchen Wang and
Shouyi Yin and
Yiyu Shi and
Shaojun Wei},
title = {A Face Alignment Accelerator Based on Optimized Coarse-to-Fine Shape
Searching},
journal = {{IEEE} Trans. Circuits Syst. Video Technol.},
volume = {29},
number = {8},
pages = {2467--2481},
year = {2019},
url = {https://doi.org/10.1109/TCSVT.2018.2867499},
doi = {10.1109/TCSVT.2018.2867499},
timestamp = {Tue, 13 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcsv/LiuWZMWYSW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tmm/MoLZYW19,
author = {Huiyu Mo and
Leibo Liu and
Wenping Zhu and
Shouyi Yin and
Shaojun Wei},
title = {Face Alignment With Expression- and Pose-Based Adaptive Initialization},
journal = {{IEEE} Trans. Multim.},
volume = {21},
number = {4},
pages = {943--956},
year = {2019},
url = {https://doi.org/10.1109/TMM.2018.2867262},
doi = {10.1109/TMM.2018.2867262},
timestamp = {Thu, 01 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tmm/MoLZYW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tpds/YinTLOTLZXLXW19,
author = {Shouyi Yin and
Shibin Tang and
Xinhan Lin and
Peng Ouyang and
Fengbin Tu and
Leibo Liu and
Jishen Zhao and
Cong Xu and
Shuangchen Li and
Yuan Xie and
Shaojun Wei},
title = {Parana: {A} Parallel Neural Architecture Considering Thermal Problem
of 3D Stacked Memory},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {30},
number = {1},
pages = {146--160},
year = {2019},
url = {https://doi.org/10.1109/TPDS.2018.2858230},
doi = {10.1109/TPDS.2018.2858230},
timestamp = {Fri, 02 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tpds/YinTLOTLZXLXW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asru/ChenYSOLW19,
author = {Xi Chen and
Shouyi Yin and
Dandan Song and
Peng Ouyang and
Leibo Liu and
Shaojun Wei},
title = {Small-Footprint Keyword Spotting with Graph Convolutional Network},
booktitle = {{IEEE} Automatic Speech Recognition and Understanding Workshop, {ASRU}
2019, Singapore, December 14-18, 2019},
pages = {539--546},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ASRU46091.2019.9004005},
doi = {10.1109/ASRU46091.2019.9004005},
timestamp = {Mon, 24 Feb 2020 17:51:31 +0100},
biburl = {https://dblp.org/rec/conf/asru/ChenYSOLW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/YanLLYW19,
author = {Hui Yan and
Zhaoshi Li and
Leibo Liu and
Shouyi Yin and
Shaojun Wei},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Constructing Concurrent Data Structures on {FPGA} with Channels},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {172--177},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293921},
doi = {10.1145/3289602.3293921},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/YanLLYW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/PanOZYZWZ19,
author = {Yu Pan and
Peng Ouyang and
Yinglin Zhao and
Shouyi Yin and
Youguang Zhang and
Shaojun Wei and
Weisheng Zhao},
editor = {Houman Homayoun and
Baris Taskin and
Tinoosh Mohsenin and
Weisheng Zhao},
title = {A Skyrmion Racetrack Memory based Computing In-memory Architecture
for Binary Neural Convolutional Network},
booktitle = {Proceedings of the 2019 on Great Lakes Symposium on VLSI, {GLSVLSI}
2019, Tysons Corner, VA, USA, May 9-11, 2019},
pages = {271--274},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3299874.3318015},
doi = {10.1145/3299874.3318015},
timestamp = {Wed, 10 Mar 2021 14:55:38 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/PanOZYZWZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hotchips/LiuLLZWSPYW19,
author = {Leibo Liu and
Ao Luo and
Guanhua Li and
Jianfeng Zhu and
Yong Wang and
Gang Shan and
Jianfeng Pan and
Shouyi Yin and
Shaojun Wei},
title = {Jintide{\textregistered}: {A} Hardware Security Enhanced Server {CPU}
with Xeon{\textregistered} Cores under Runtime Surveillance by an
In-Package Dynamically Reconfigurable Processor},
booktitle = {2019 {IEEE} Hot Chips 31 Symposium (HCS), Cupertino, CA, USA, August
18-20, 2019},
pages = {1--25},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/HOTCHIPS.2019.8875682},
doi = {10.1109/HOTCHIPS.2019.8875682},
timestamp = {Sun, 16 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hotchips/LiuLLZWSPYW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/LuLLWYW19,
author = {Kai Lu and
Zhaoshi Li and
Leibo Liu and
Jiawei Wang and
Shouyi Yin and
Shaojun Wei},
editor = {David Z. Pan},
title = {ReDESK: {A} Reconfigurable Dataflow Engine for Sparse Kernels on Heterogeneous
Platforms},
booktitle = {Proceedings of the International Conference on Computer-Aided Design,
{ICCAD} 2019, Westminster, CO, USA, November 4-7, 2019},
pages = {1--8},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1109/ICCAD45719.2019.8942089},
doi = {10.1109/ICCAD45719.2019.8942089},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/LuLLWYW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/YuanGC0WYDLGZ19,
author = {Hang Yuan and
Wei Guo and
Chip{-}Hong Chang and
Yuan Cao and
Shaojun Wei and
Shouyi Yin and
Chenchen Deng and
Leibo Liu and
Wei Ge and
Fan Zhang},
title = {A Reliable Physical Unclonable Function Based on Differential Charging
Capacitors},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2019,
Sapporo, Japan, May 26-29, 2019},
pages = {1--5},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISCAS.2019.8702728},
doi = {10.1109/ISCAS.2019.8702728},
timestamp = {Wed, 07 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/YuanGC0WYDLGZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/YangKWLWYS19,
author = {Jun Yang and
Yuyao Kong and
Zhen Wang and
Yan Liu and
Bo Wang and
Shouyi Yin and
Longxin Shi},
title = {Sandwich-RAM: An Energy-Efficient In-Memory {BWN} Architecture with
Pulse-Width Modulation},
booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2019,
San Francisco, CA, USA, February 17-21, 2019},
pages = {394--396},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISSCC.2019.8662435},
doi = {10.1109/ISSCC.2019.8662435},
timestamp = {Mon, 02 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/YangKWLWYS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/XiongTYW19,
author = {Feng Xiong and
Fengbin Tu and
Shouyi Yin and
Shaojun Wei},
title = {Towards Efficient Compact Network Training on Edge-Devices},
booktitle = {2019 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2019,
Miami, FL, USA, July 15-17, 2019},
pages = {61--67},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISVLSI.2019.00020},
doi = {10.1109/ISVLSI.2019.00020},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/isvlsi/XiongTYW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/LiLDWLYW19,
author = {Zhaoshi Li and
Leibo Liu and
Yangdong Deng and
Jiawei Wang and
Zhiwei Liu and
Shouyi Yin and
Shaojun Wei},
title = {FPGA-Accelerated Optimistic Concurrency Control for Transactional
Memory},
booktitle = {Proceedings of the 52nd Annual {IEEE/ACM} International Symposium
on Microarchitecture, {MICRO} 2019, Columbus, OH, USA, October 12-16,
2019},
pages = {911--923},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3352460.3358270},
doi = {10.1145/3352460.3358270},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/micro/LiLDWLYW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nanoarch/YangLZWY19,
author = {Jianxun Yang and
Leibo Liu and
Jin Zhang and
Shaojun Wei and
Shouyi Yin},
title = {An Energy-Efficient Architecture for Accelerating Inference of Memory-Augmented
Neural Networks},
booktitle = {{IEEE/ACM} International Symposium on Nanoscale Architectures, {NANOARCH}
2019, Qingdao, China, July 17-19, 2019},
pages = {1--6},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/NANOARCH47378.2019.181289},
doi = {10.1109/NANOARCH47378.2019.181289},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/nanoarch/YangLZWY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/newcas/WuYTLW19,
author = {Weiwei Wu and
Shouyi Yin and
Fengbin Tu and
Leibo Liu and
Shaojun Wei},
title = {MoNA: Mobile Neural Architecture with Reconfigurable Parallel Dimensions},
booktitle = {17th {IEEE} International New Circuits and Systems Conference, {NEWCAS}
2019, Munich, Germany, June 23-26, 2019},
pages = {1--4},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/NEWCAS44328.2019.8961273},
doi = {10.1109/NEWCAS44328.2019.8961273},
timestamp = {Tue, 04 Feb 2020 14:36:47 +0100},
biburl = {https://dblp.org/rec/conf/newcas/WuYTLW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/GuoLZWOKCCLLCWY19,
author = {Ruiqi Guo and
Yonggang Liu and
Shixuan Zheng and
Ssu{-}Yen Wu and
Peng Ouyang and
Win{-}San Khwa and
Xi Chen and
Jia{-}Jing Chen and
Xiudong Li and
Leibo Liu and
Meng{-}Fan Chang and
Shaojun Wei and
Shouyi Yin},
title = {A 5.1pJ/Neuron 127.3us/Inference RNN-based Speech Recognition Processor
using 16 Computing-in-Memory {SRAM} Macros in 65nm {CMOS}},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {120},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778028},
doi = {10.23919/VLSIC.2019.8778028},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/GuoLZWOKCCLLCWY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1912-05124,
author = {Xi Chen and
Shouyi Yin and
Dandan Song and
Peng Ouyang and
Leibo Liu and
Shaojun Wei},
title = {Small-footprint Keyword Spotting with Graph Convolutional Network},
journal = {CoRR},
volume = {abs/1912.05124},
year = {2019},
url = {http://arxiv.org/abs/1912.05124},
eprinttype = {arXiv},
eprint = {1912.05124},
timestamp = {Thu, 02 Jan 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-1912-05124.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1912-11585,
author = {Yi Liu and
Tianyu Liang and
Can Xu and
Xianwei Zhang and
Xianhong Chen and
Wei{-}Qiang Zhang and
Liang He and
Dandan Song and
Ruyun Li and
Yangcheng Wu and
Peng Ouyang and
Shouyi Yin},
title = {{THUEE} system description for {NIST} 2019 {SRE} {CTS} Challenge},
journal = {CoRR},
volume = {abs/1912.11585},
year = {2019},
url = {http://arxiv.org/abs/1912.11585},
eprinttype = {arXiv},
eprint = {1912.11585},
timestamp = {Tue, 01 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1912-11585.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/YinLYXLW18,
author = {Shouyi Yin and
Tianyi Lu and
Xianqing Yao and
Zhicong Xie and
Leibo Liu and
Shaojun Wei},
title = {Multi-Bank Memory Aware Force Directed Scheduling for High-Level Synthesis},
journal = {{IEEE} Access},
volume = {6},
pages = {7526--7540},
year = {2018},
url = {https://doi.org/10.1109/ACCESS.2018.2798586},
doi = {10.1109/ACCESS.2018.2798586},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/access/YinLYXLW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cal/LiLDYW18,
author = {Zhaoshi Li and
Leibo Liu and
Yangdong Deng and
Shouyi Yin and
Shaojun Wei},
title = {Breaking the Synchronization Bottleneck with Reconfigurable Transactional
Execution},
journal = {{IEEE} Comput. Archit. Lett.},
volume = {17},
number = {2},
pages = {147--150},
year = {2018},
url = {https://doi.org/10.1109/LCA.2018.2828402},
doi = {10.1109/LCA.2018.2828402},
timestamp = {Sun, 15 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/cal/LiLDYW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijon/LiangYLLW18,
author = {Shuang Liang and
Shouyi Yin and
Leibo Liu and
Wayne Luk and
Shaojun Wei},
title = {{FP-BNN:} Binarized neural network on {FPGA}},
journal = {Neurocomputing},
volume = {275},
pages = {1072--1086},
year = {2018},
url = {https://doi.org/10.1016/j.neucom.2017.09.046},
doi = {10.1016/J.NEUCOM.2017.09.046},
timestamp = {Thu, 22 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ijon/LiangYLLW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jolpe/HuTYW18,
author = {Ruofei Hu and
Binren Tian and
Shouyi Yin and
Shaojun Wei},
title = {Optimization of Softmax Layer in Deep Neural Network Using Integral
Stochastic Computation},
journal = {J. Low Power Electron.},
volume = {14},
number = {4},
pages = {475--480},
year = {2018},
url = {https://doi.org/10.1166/jolpe.2018.1579},
doi = {10.1166/JOLPE.2018.1579},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jolpe/HuTYW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/YinOTTLZLGLW18,
author = {Shouyi Yin and
Peng Ouyang and
Shibin Tang and
Fengbin Tu and
Xiudong Li and
Shixuan Zheng and
Tianyi Lu and
Jiangyuan Gu and
Leibo Liu and
Shaojun Wei},
title = {A High Energy Efficient Reconfigurable Hybrid Neural Network Processor
for Deep Learning Applications},
journal = {{IEEE} J. Solid State Circuits},
volume = {53},
number = {4},
pages = {968--982},
year = {2018},
url = {https://doi.org/10.1109/JSSC.2017.2778281},
doi = {10.1109/JSSC.2017.2778281},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/YinOTTLZLGLW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YinXMOLW18,
author = {Shouyi Yin and
Zhicong Xie and
Chenyue Meng and
Peng Ouyang and
Leibo Liu and
Shaojun Wei},
title = {Memory Partitioning for Parallel Multipattern Data Access in Multiple
Data Arrays},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {2},
pages = {431--444},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2693274},
doi = {10.1109/TCAD.2017.2693274},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YinXMOLW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuZWZYM18,
author = {Leibo Liu and
Zhuoquan Zhou and
Shaojun Wei and
Min Zhu and
Shouyi Yin and
Shengyang Mao},
title = {DRMaSV: Enhanced Capability Against Hardware Trojans in Coarse Grained
Reconfigurable Architectures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {4},
pages = {782--795},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2729340},
doi = {10.1109/TCAD.2017.2729340},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuZWZYM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuYYW18,
author = {Leibo Liu and
Chen Yang and
Shouyi Yin and
Shaojun Wei},
title = {{CDPM:} Context-Directed Pattern Matching Prefetching to Improve Coarse-Grained
Reconfigurable Array Performance},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {6},
pages = {1171--1184},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2748026},
doi = {10.1109/TCAD.2017.2748026},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuYYW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YanYTLW18,
author = {Jiale Yan and
Shouyi Yin and
Fengbin Tu and
Leibo Liu and
Shaojun Wei},
title = {{GNA:} Reconfigurable and Efficient Architecture for Generative Network
Acceleration},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2519--2529},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857258},
doi = {10.1109/TCAD.2018.2857258},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YanYTLW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuWDZYW18,
author = {Leibo Liu and
Bo Wang and
Chenchen Deng and
Min Zhu and
Shouyi Yin and
Shaojun Wei},
title = {Anole: {A} Highly Efficient Dynamically Reconfigurable Crypto-Processor
for Symmetric-Key Algorithms},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {12},
pages = {3081--3094},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2801229},
doi = {10.1109/TCAD.2018.2801229},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuWDZYW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/LiuLYDYW18,
author = {Leibo Liu and
Zhaoshi Li and
Chen Yang and
Chenchen Deng and
Shouyi Yin and
Shaojun Wei},
title = {HReA: An Energy-Efficient Embedded Dynamically Reconfigurable Fabric
for 13-Dwarfs Processing},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {65-II},
number = {3},
pages = {381--385},
year = {2018},
url = {https://doi.org/10.1109/TCSII.2017.2728814},
doi = {10.1109/TCSII.2017.2728814},
timestamp = {Wed, 27 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/LiuLYDYW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/PengLZYW18,
author = {Guiqiang Peng and
Leibo Liu and
Sheng Zhou and
Shouyi Yin and
Shaojun Wei},
title = {A 1.58 Gbps/W 0.40 Gbps/mm2 {ASIC} Implementation of {MMSE} Detection
for {\textdollar}128{\textbackslash}times 8{\textasciitilde}64{\textdollar}
-QAM Massive {MIMO} in 65 nm {CMOS}},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {65-I},
number = {5},
pages = {1717--1730},
year = {2018},
url = {https://doi.org/10.1109/TCSI.2017.2754282},
doi = {10.1109/TCSI.2017.2754282},
timestamp = {Wed, 22 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcas/PengLZYW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/OuyangYLZZW18,
author = {Peng Ouyang and
Shouyi Yin and
Leibo Liu and
Youguang Zhang and
Weisheng Zhao and
Shaojun Wei},
title = {A Fast and Power-Efficient Hardware Architecture for Visual Feature
Detection in Affine-SIFT},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {65-I},
number = {10},
pages = {3362--3375},
year = {2018},
url = {https://doi.org/10.1109/TCSI.2018.2806447},
doi = {10.1109/TCSI.2018.2806447},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/OuyangYLZZW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tpds/GuYLW18,
author = {Jiangyuan Gu and
Shouyi Yin and
Leibo Liu and
Shaojun Wei},
title = {Stress-Aware Loops Mapping on CGRAs with Dynamic Multi-Map Reconfiguration},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {29},
number = {9},
pages = {2105--2120},
year = {2018},
url = {https://doi.org/10.1109/TPDS.2018.2816955},
doi = {10.1109/TPDS.2018.2816955},
timestamp = {Fri, 02 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tpds/GuYLW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tpds/LuLDWYSW18,
author = {Yanan Lu and
Leibo Liu and
Yangdong Deng and
Jian Weng and
Shouyi Yin and
Yiyu Shi and
Shaojun Wei},
title = {Triggered-Issuance and Triggered-Execution: {A} Control Paradigm to
Minimize Pipeline Stalls in Distributed Controlled Coarse-Grained
Reconfigurable Arrays},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {29},
number = {10},
pages = {2360--2372},
year = {2018},
url = {https://doi.org/10.1109/TPDS.2018.2822708},
doi = {10.1109/TPDS.2018.2822708},
timestamp = {Tue, 13 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tpds/LuLDWYSW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tsp/PengLZXYW18,
author = {Guiqiang Peng and
Leibo Liu and
Sheng Zhou and
Yang Xue and
Shouyi Yin and
Shaojun Wei},
title = {Algorithm and Architecture of a Low-Complexity and High-Parallelism
Preprocessing-Based {K} -Best Detector for Large-Scale {MIMO} Systems},
journal = {{IEEE} Trans. Signal Process.},
volume = {66},
number = {7},
pages = {1860--1875},
year = {2018},
url = {https://doi.org/10.1109/TSP.2018.2799191},
doi = {10.1109/TSP.2018.2799191},
timestamp = {Wed, 22 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tsp/PengLZXYW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YinLXLW18,
author = {Shouyi Yin and
Tianyi Lu and
Zhicong Xie and
Leibo Liu and
Shaojun Wei},
title = {Bit-Level Disturbance-Aware Memory Partitioning for Parallel Data
Access for {MLC} {STT-RAM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {11},
pages = {2345--2357},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2862388},
doi = {10.1109/TVLSI.2018.2862388},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YinLXLW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/WangSZCRWYJLHYW18,
author = {Hang Wang and
Hongbin Sun and
Xuchong Zhang and
Qiubo Chen and
Pengju Ren and
Xiaogang Wu and
Shouyi Yin and
Zhiqiang Jiang and
Xiang Li and
Daqiang Han and
Shiquan Yu and
Shaojun Wei and
Nanning Zheng},
title = {A 4K{\texttimes}2K@60fps Multi-format Multi-function Display Processor
for High Perceptual Quality},
booktitle = {2018 {IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS}
2018, Chengdu, China, October 26-30, 2018},
pages = {427--430},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/APCCAS.2018.8605706},
doi = {10.1109/APCCAS.2018.8605706},
timestamp = {Wed, 26 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/apccas/WangSZCRWYJLHYW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/PengLWWYW18,
author = {Guiqiang Peng and
Leibo Liu and
Qiushi Wei and
Yao Wang and
Shouyi Yin and
Shaojun Wei},
title = {A 2.69 Mbps/mW 1.09 Mbps/kGE Conjugate Gradient-based {MMSE} Detector
for 64-QAM 128{\texttimes}8 Massive {MIMO} Systems},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2018, Tainan,
Taiwan, November 5-7, 2018},
pages = {191--194},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ASSCC.2018.8579260},
doi = {10.1109/ASSCC.2018.8579260},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asscc/PengLWWYW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cyberc/YuanLLYW18,
author = {Hang Yuan and
Leibo Liu and
Hui Li and
Shouyi Yin and
Shaojun Wei},
title = {A Full Multicast Reconfigurable Non-blocking Permutation Network},
booktitle = {International Conference on Cyber-Enabled Distributed Computing and
Knowledge Discovery, CyberC 2018, Zhengzhou, China, October 18-20,
2018},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/CyberC.2018.00092},
doi = {10.1109/CYBERC.2018.00092},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cyberc/YuanLLYW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/LinYTLLW18,
author = {Xinhan Lin and
Shouyi Yin and
Fengbin Tu and
Leibo Liu and
Xiangyu Li and
Shaojun Wei},
title = {{LCP:} a layer clusters paralleling mapping method for accelerating
inception and residual networks on {FPGA}},
booktitle = {Proceedings of the 55th Annual Design Automation Conference, {DAC}
2018, San Francisco, CA, USA, June 24-29, 2018},
pages = {16:1--16:6},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3195970.3196067},
doi = {10.1145/3195970.3196067},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/LinYTLLW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/ZhengLYLW18,
author = {Shixuan Zheng and
Yonggang Liu and
Shouyi Yin and
Leibo Liu and
Shaojun Wei},
title = {An efficient kernel transformation architecture for binary- and ternary-weight
neural network inference},
booktitle = {Proceedings of the 55th Annual Design Automation Conference, {DAC}
2018, San Francisco, CA, USA, June 24-29, 2018},
pages = {137:1--137:6},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3195970.3195988},
doi = {10.1145/3195970.3195988},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/ZhengLYLW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icdsp/HuTYW18,
author = {Ruofei Hu and
Binren Tian and
Shouyi Yin and
Shaojun Wei},
title = {Efficient Hardware Architecture of Softmax Layer in Deep Neural Network},
booktitle = {23rd {IEEE} International Conference on Digital Signal Processing,
{DSP} 2018, Shanghai, China, November 19-21, 2018},
pages = {1--5},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ICDSP.2018.8631588},
doi = {10.1109/ICDSP.2018.8631588},
timestamp = {Mon, 31 Oct 2022 09:05:23 +0100},
biburl = {https://dblp.org/rec/conf/icdsp/HuTYW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/TuWYLW18,
author = {Fengbin Tu and
Weiwei Wu and
Shouyi Yin and
Leibo Liu and
Shaojun Wei},
editor = {Murali Annavaram and
Timothy Mark Pinkston and
Babak Falsafi},
title = {{RANA:} Towards Efficient Neural Acceleration with Refresh-Optimized
Embedded {DRAM}},
booktitle = {45th {ACM/IEEE} Annual International Symposium on Computer Architecture,
{ISCA} 2018, Los Angeles, CA, USA, June 1-6, 2018},
pages = {340--352},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/ISCA.2018.00037},
doi = {10.1109/ISCA.2018.00037},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isca/TuWYLW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/GuoYOTTLW18,
author = {Jianxin Guo and
Shouyi Yin and
Peng Ouyang and
Fengbin Tu and
Shibin Tang and
Leibo Liu and
Shaojun Wei},
title = {Bit-width Adaptive Accelerator Design for Convolution Neural Network},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2018,
27-30 May 2018, Florence, Italy},
pages = {1--5},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISCAS.2018.8351666},
doi = {10.1109/ISCAS.2018.8351666},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/GuoYOTTLW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/WangYTLW18,
author = {Zhihui Wang and
Shouyi Yin and
Fengbin Tu and
Leibo Liu and
Shaojun Wei},
title = {An Energy Efficient {JPEG} Encoder with Neural Network Based Approximation
and Near-Threshold Computing},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2018,
27-30 May 2018, Florence, Italy},
pages = {1--5},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISCAS.2018.8350956},
doi = {10.1109/ISCAS.2018.8350956},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/WangYTLW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/YinOYLLLW18,
author = {Shouyi Yin and
Peng Ouyang and
Jianxun Yang and
Tianyi Lu and
Xiudong Li and
Leibo Liu and
Shaojun Wei},
title = {An Ultra-High Energy-Efficient Reconfigurable Processor for Deep Neural
Networks with Binary/Ternary Weights in 28NM {CMOS}},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {37--38},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502388},
doi = {10.1109/VLSIC.2018.8502388},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/YinOYLLLW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/YinOZSLLW18,
author = {Shouyi Yin and
Peng Ouyang and
Shixuan Zheng and
Dandan Song and
Xiudong Li and
Leibo Liu and
Shaojun Wei},
title = {A 141 UW, 2.46 PJ/Neuron Binarized Convolutional Neural Network Based
Self-Learning Speech Recognition Processor in 28NM {CMOS}},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {139--140},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502309},
doi = {10.1109/VLSIC.2018.8502309},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/YinOZSLLW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/XuYZDSLW17,
author = {Weizhi Xu and
Shouyi Yin and
Zhen Zhang and
Hao Dong and
Rui Shi and
Leibo Liu and
Shaojun Wei},
title = {Reconfigurable {VLSI} Architecture for Real-Time 2D-to-3D Conversion},
journal = {{IEEE} Access},
volume = {5},
pages = {26604--26613},
year = {2017},
url = {https://doi.org/10.1109/ACCESS.2017.2778220},
doi = {10.1109/ACCESS.2017.2778220},
timestamp = {Fri, 14 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/access/XuYZDSLW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-ipr/LiuCDYW17,
author = {Leibo Liu and
Yingjie Chen and
Chenchen Deng and
Shouyi Yin and
Shaojun Wei},
title = {Implementation of in-loop filter for {HEVC} decoder on reconfigurable
processor},
journal = {{IET} Image Process.},
volume = {11},
number = {9},
pages = {685--692},
year = {2017},
url = {https://doi.org/10.1049/iet-ipr.2016.0143},
doi = {10.1049/IET-IPR.2016.0143},
timestamp = {Thu, 18 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-ipr/LiuCDYW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sj/YinODLW17,
author = {Shouyi Yin and
Peng Ouyang and
Xu Dai and
Leibo Liu and
Shaojun Wei},
title = {An AdaBoost-Based Face Detection System Using Parallel Configurable
Architecture With Optimized Computation},
journal = {{IEEE} Syst. J.},
volume = {11},
number = {1},
pages = {260--271},
year = {2017},
url = {https://doi.org/10.1109/JSYST.2015.2418680},
doi = {10.1109/JSYST.2015.2418680},
timestamp = {Fri, 11 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/sj/YinODLW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/DengLLYW17,
author = {Chenchen Deng and
Leibo Liu and
Yang Liu and
Shouyi Yin and
Shaojun Wei},
title = {{PMCC:} Fast and Accurate System-Level Power Modeling for Processors
on Heterogeneous SoC},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {64-II},
number = {5},
pages = {540--544},
year = {2017},
url = {https://doi.org/10.1109/TCSII.2016.2615930},
doi = {10.1109/TCSII.2016.2615930},
timestamp = {Wed, 27 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/DengLLYW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tifs/WangLDZYZW17,
author = {Bo Wang and
Leibo Liu and
Chenchen Deng and
Min Zhu and
Shouyi Yin and
Zhuoquan Zhou and
Shaojun Wei},
title = {Exploration of Benes Network in Cryptographic Processors: {A} Random
Infection Countermeasure for Block Ciphers Against Fault Attacks},
journal = {{IEEE} Trans. Inf. Forensics Secur.},
volume = {12},
number = {2},
pages = {309--322},
year = {2017},
url = {https://doi.org/10.1109/TIFS.2016.2612638},
doi = {10.1109/TIFS.2016.2612638},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tifs/WangLDZYZW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tpds/YangLLYW17,
author = {Chen Yang and
Leibo Liu and
Kai Luo and
Shouyi Yin and
Shaojun Wei},
title = {{CIACP:} {A} Correlation- and Iteration- Aware Cache Partitioning
Mechanism to Improve Performance of Multiple Coarse-Grained Reconfigurable
Arrays},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {28},
number = {1},
pages = {29--43},
year = {2017},
url = {https://doi.org/10.1109/TPDS.2016.2554278},
doi = {10.1109/TPDS.2016.2554278},
timestamp = {Fri, 02 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tpds/YangLLYW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tpds/WuDLHCYW17,
author = {Chen Wu and
Chenchen Deng and
Leibo Liu and
Jie Han and
Jiqiang Chen and
Shouyi Yin and
Shaojun Wei},
title = {A Multi-Objective Model Oriented Mapping Approach for NoC-based Computing
Systems},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {28},
number = {3},
pages = {662--676},
year = {2017},
url = {https://doi.org/10.1109/TPDS.2016.2589934},
doi = {10.1109/TPDS.2016.2589934},
timestamp = {Fri, 02 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tpds/WuDLHCYW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tpds/YinYLLGLW17,
author = {Shouyi Yin and
Xianqing Yao and
Tianyi Lu and
Dajiang Liu and
Jiangyuan Gu and
Leibo Liu and
Shaojun Wei},
title = {Conflict-Free Loop Mapping for Coarse-Grained Reconfigurable Architecture
with Multi-Bank Memory},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {28},
number = {9},
pages = {2471--2485},
year = {2017},
url = {https://doi.org/10.1109/TPDS.2017.2682241},
doi = {10.1109/TPDS.2017.2682241},
timestamp = {Fri, 02 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tpds/YinYLLGLW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tsp/PengLZYW17,
author = {Guiqiang Peng and
Leibo Liu and
Peng Zhang and
Shouyi Yin and
Shaojun Wei},
title = {Low-Computing-Load, High-Parallelism Detection Method Based on Chebyshev
Iteration for Massive {MIMO} Systems With {VLSI} Architecture},
journal = {{IEEE} Trans. Signal Process.},
volume = {65},
number = {14},
pages = {3775--3788},
year = {2017},
url = {https://doi.org/10.1109/TSP.2017.2698410},
doi = {10.1109/TSP.2017.2698410},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tsp/PengLZYW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TuYOTLW17,
author = {Fengbin Tu and
Shouyi Yin and
Peng Ouyang and
Shibin Tang and
Leibo Liu and
Shaojun Wei},
title = {Deep Convolutional Neural Network Architecture With Reconfigurable
Computation Patterns},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {8},
pages = {2220--2233},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2688340},
doi = {10.1109/TVLSI.2017.2688340},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TuYOTLW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/GuYLW17,
author = {Jiangyuan Gu and
Shouyi Yin and
Leibo Liu and
Shaojun Wei},
title = {Energy-aware loops mapping on multi-vdd CGRAs without performance
degradation},
booktitle = {22nd Asia and South Pacific Design Automation Conference, {ASP-DAC}
2017, Chiba, Japan, January 16-19, 2017},
pages = {312--317},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ASPDAC.2017.7858341},
doi = {10.1109/ASPDAC.2017.7858341},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/GuYLW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/GuYW17,
author = {Jiangyuan Gu and
Shouyi Yin and
Shaojun Wei},
title = {Stress-Aware Loops Mapping on CGRAs with Considering {NBTI} Aging
Effect},
booktitle = {Proceedings of the 54th Annual Design Automation Conference, {DAC}
2017, Austin, TX, USA, June 18-22, 2017},
pages = {40:1--40:6},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3061639.3062322},
doi = {10.1145/3061639.3062322},
timestamp = {Tue, 06 Nov 2018 16:58:15 +0100},
biburl = {https://dblp.org/rec/conf/dac/GuYW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/OuyangYW17,
author = {Peng Ouyang and
Shouyi Yin and
Shaojun Wei},
title = {A Fast and Power Efficient Architecture to Parallelize {LSTM} based
{RNN} for Cognitive Intelligence Applications},
booktitle = {Proceedings of the 54th Annual Design Automation Conference, {DAC}
2017, Austin, TX, USA, June 18-22, 2017},
pages = {63:1--63:6},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3061639.3062187},
doi = {10.1145/3061639.3062187},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/OuyangYW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/YinXW17,
author = {Shouyi Yin and
Zhicong Xie and
Shaojun Wei},
title = {Disturbance Aware Memory Partitioning for Parallel Data Access in
{STT-RAM}},
booktitle = {Proceedings of the 54th Annual Design Automation Conference, {DAC}
2017, Austin, TX, USA, June 18-22, 2017},
pages = {84:1--84:6},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3061639.3062232},
doi = {10.1145/3061639.3062232},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/YinXW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/GuoYOLW17,
author = {Jianxin Guo and
Shouyi Yin and
Peng Ouyang and
Leibo Liu and
Shaojun Wei},
title = {Bit-Width Based Resource Partitioning for {CNN} Acceleration on {FPGA}},
booktitle = {25th {IEEE} Annual International Symposium on Field-Programmable Custom
Computing Machines, {FCCM} 2017, Napa, CA, USA, April 30 - May 2,
2017},
pages = {31},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/FCCM.2017.13},
doi = {10.1109/FCCM.2017.13},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/GuoYOLW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/LuYYXLW17,
author = {Tianyi Lu and
Shouyi Yin and
Xianqing Yao and
Zhicong Xie and
Leibo Liu and
Shaojun Wei},
editor = {Jonathan W. Greene and
Jason Helge Anderson},
title = {Joint Modulo Scheduling and Memory Partitioning with Multi-Bank Memory
for High-Level Synthesis (Abstract Only)},
booktitle = {Proceedings of the 2017 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2017, Monterey, CA, USA, February 22-24, 2017},
pages = {290},
publisher = {{ACM}},
year = {2017},
url = {http://dl.acm.org/citation.cfm?id=3021778},
timestamp = {Tue, 06 Nov 2018 16:58:22 +0100},
biburl = {https://dblp.org/rec/conf/fpga/LuYYXLW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/YinLSLLW17,
author = {Shouyi Yin and
Dajiang Liu and
Lifeng Sun and
Xinhan Lin and
Leibo Liu and
Shaojun Wei},
editor = {Jonathan W. Greene and
Jason Helge Anderson},
title = {Learning Convolutional Neural Networks for Data-Flow Graph Mapping
on Spatial Programmable Architectures (Abstract Only)},
booktitle = {Proceedings of the 2017 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2017, Monterey, CA, USA, February 22-24, 2017},
pages = {295},
publisher = {{ACM}},
year = {2017},
url = {http://dl.acm.org/citation.cfm?id=3021801},
timestamp = {Fri, 03 Feb 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/YinLSLLW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/OuyangYXLW17,
author = {Peng Ouyang and
Shouyi Yin and
Chunxiao Xing and
Leibo Liu and
Shaojun Wei},
editor = {Laleh Behjat and
Jie Han and
Miroslav N. Velev and
Deming Chen},
title = {A Power Efficient Architecture with Optimized Parallel Memory Accessing
for Feature Generation},
booktitle = {Proceedings of the on Great Lakes Symposium on {VLSI} 2017, Banff,
AB, Canada, May 10-12, 2017},
pages = {287--292},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3060403.3060436},
doi = {10.1145/3060403.3060436},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/OuyangYXLW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/LiLDYWW17,
author = {Zhaoshi Li and
Leibo Liu and
Yangdong Deng and
Shouyi Yin and
Yao Wang and
Shaojun Wei},
title = {Aggressive Pipelining of Irregular Applications on Reconfigurable
Hardware},
booktitle = {Proceedings of the 44th Annual International Symposium on Computer
Architecture, {ISCA} 2017, Toronto, ON, Canada, June 24-28, 2017},
pages = {575--586},
publisher = {{ACM}},
year = {2017},
url = {https://dl.acm.org/citation.cfm?id=3080228},
timestamp = {Mon, 26 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isca/LiLDYWW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/LuYYXLW17,
author = {Tianyi Lu and
Shouyi Yin and
Xianqing Yao and
Zhicong Xie and
Leibo Liu and
Shaojun Wei},
title = {Memory fartitioning-based modulo scheduling for high-level synthesis},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2017,
Baltimore, MD, USA, May 28-31, 2017},
pages = {1--4},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISCAS.2017.8050969},
doi = {10.1109/ISCAS.2017.8050969},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/LuYYXLW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/YinLSLW17,
author = {Shouyi Yin and
Dajiang Liu and
Lifeng Sun and
Leibo Liu and
Shaojun Wei},
title = {DFGNet: Mapping dataflow graph onto {CGRA} by a deep learning approach},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2017,
Baltimore, MD, USA, May 28-31, 2017},
pages = {1--4},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISCAS.2017.8050274},
doi = {10.1109/ISCAS.2017.8050274},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/YinLSLW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nvmsa/TangYZOTYWCLW17,
author = {Shibin Tang and
Shouyi Yin and
Shixuan Zheng and
Peng Ouyang and
Fengbin Tu and
Leiyue Yao and
JinZhou Wu and
Wenming Cheng and
Leibo Liu and
Shaojun Wei},
title = {{AEPE:} An area and power efficient {RRAM} crossbar-based accelerator
for deep CNNs},
booktitle = {{IEEE} 6th Non-Volatile Memory Systems and Applications Symposium,
{NVMSA} 2017, Hsinchu, Taiwan, August 16-18, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/NVMSA.2017.8064475},
doi = {10.1109/NVMSA.2017.8064475},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/nvmsa/TangYZOTYWCLW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sac/YinDOLW17,
author = {Shouyi Yin and
Jinjin Duan and
Peng Ouyang and
Leibo Liu and
Shaojun Wei},
editor = {Ahmed Seffah and
Birgit Penzenstadler and
Carina Alves and
Xin Peng},
title = {Multi-CNN and decision tree based driving behavior evaluation},
booktitle = {Proceedings of the Symposium on Applied Computing, {SAC} 2017, Marrakech,
Morocco, April 3-7, 2017},
pages = {1424--1429},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3019612.3019649},
doi = {10.1145/3019612.3019649},
timestamp = {Wed, 01 Feb 2023 17:58:48 +0100},
biburl = {https://dblp.org/rec/conf/sac/YinDOLW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cal/LiangYLGW16,
author = {Shuang Liang and
Shouyi Yin and
Leibo Liu and
Yike Guo and
Shaojun Wei},
title = {A Coarse-Grained Reconfigurable Architecture for Compute-Intensive
MapReduce Acceleration},
journal = {{IEEE} Comput. Archit. Lett.},
volume = {15},
number = {2},
pages = {69--72},
year = {2016},
url = {https://doi.org/10.1109/LCA.2015.2458318},
doi = {10.1109/LCA.2015.2458318},
timestamp = {Thu, 22 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/cal/LiangYLGW16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/chinaf/OuyangYDLW16,
author = {Peng Ouyang and
Shouyi Yin and
Chenchen Deng and
Leibo Liu and
Shaojun Wei},
title = {A fast face detection architecture for auto-focus in smart-phones
and digital cameras},
journal = {Sci. China Inf. Sci.},
volume = {59},
number = {12},
pages = {122402:1--122402:13},
year = {2016},
url = {https://doi.org/10.1007/s11432-015-5312-z},
doi = {10.1007/S11432-015-5312-Z},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/chinaf/OuyangYDLW16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/LiuWCZYW16,
author = {Leibo Liu and
Dong Wang and
Yingjie Chen and
Min Zhu and
Shouyi Yin and
Shaojun Wei},
title = {An Implementation of Multiple-Standard Video Decoder on a Mixed-Grained
Reconfigurable Computing Platform},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {99-D},
number = {5},
pages = {1285--1295},
year = {2016},
url = {https://doi.org/10.1587/transinf.2015EDP7369},
doi = {10.1587/TRANSINF.2015EDP7369},
timestamp = {Sat, 22 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/LiuWCZYW16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YinGLLW16,
author = {Shouyi Yin and
Jiangyuan Gu and
Dajiang Liu and
Leibo Liu and
Shaojun Wei},
title = {Joint Modulo Scheduling and V\({}_{\mbox{dd}}\) Assignment for Loop
Mapping on Dual- V\({}_{\mbox{dd}}\) CGRAs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {35},
number = {9},
pages = {1475--1488},
year = {2016},
url = {https://doi.org/10.1109/TCAD.2015.2512900},
doi = {10.1109/TCAD.2015.2512900},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YinGLLW16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/YinOLW16,
author = {Shouyi Yin and
Peng Ouyang and
Leibo Liu and
Shaojun Wei},
title = {A Fast and Power-Efficient Memory-Centric Architecture for Affine
Computation},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {63-II},
number = {7},
pages = {668--672},
year = {2016},
url = {https://doi.org/10.1109/TCSII.2016.2530168},
doi = {10.1109/TCSII.2016.2530168},
timestamp = {Wed, 27 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/YinOLW16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcsv/ZhuLJYW16,
author = {Wenping Zhu and
Leibo Liu and
Guangli Jiang and
Shouyi Yin and
Shaojun Wei},
title = {A 135-frames/s 1080p 87.5-mW Binary-Descriptor-Based Image Feature
Extraction Accelerator},
journal = {{IEEE} Trans. Circuits Syst. Video Technol.},
volume = {26},
number = {8},
pages = {1532--1543},
year = {2016},
url = {https://doi.org/10.1109/TCSVT.2015.2469116},
doi = {10.1109/TCSVT.2015.2469116},
timestamp = {Tue, 25 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcsv/ZhuLJYW16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tifs/WangLDZYW16,
author = {Bo Wang and
Leibo Liu and
Chenchen Deng and
Min Zhu and
Shouyi Yin and
Shaojun Wei},
title = {Against Double Fault Attacks: Injection Effort Model, Space and Time
Randomization Based Countermeasures for Reconfigurable Array Architecture},
journal = {{IEEE} Trans. Inf. Forensics Secur.},
volume = {11},
number = {6},
pages = {1151--1164},
year = {2016},
url = {https://doi.org/10.1109/TIFS.2016.2518130},
doi = {10.1109/TIFS.2016.2518130},
timestamp = {Thu, 06 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tifs/WangLDZYW16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tpds/LiuWZDYW16,
author = {Leibo Liu and
Junbin Wang and
Jianfeng Zhu and
Chenchen Deng and
Shouyi Yin and
Shaojun Wei},
title = {{TLIA:} Efficient Reconfigurable Architecture for Control-Intensive
Kernels with Triggered-Long-Instructions},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {27},
number = {7},
pages = {2143--2154},
year = {2016},
url = {https://doi.org/10.1109/TPDS.2015.2477841},
doi = {10.1109/TPDS.2015.2477841},
timestamp = {Fri, 02 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tpds/LiuWZDYW16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tpds/YinLLW16,
author = {Shouyi Yin and
Xinhan Lin and
Leibo Liu and
Shaojun Wei},
title = {Exploiting Parallelism of Imperfect Nested Loops on Coarse-Grained
Reconfigurable Architectures},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {27},
number = {11},
pages = {3199--3213},
year = {2016},
url = {https://doi.org/10.1109/TPDS.2016.2531678},
doi = {10.1109/TPDS.2016.2531678},
timestamp = {Fri, 02 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tpds/YinLLW16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YinLPLW16,
author = {Shouyi Yin and
Dajiang Liu and
Yu Peng and
Leibo Liu and
Shaojun Wei},
title = {Improving Nested Loop Pipelining on Coarse-Grained Reconfigurable
Architectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {24},
number = {2},
pages = {507--520},
year = {2016},
url = {https://doi.org/10.1109/TVLSI.2015.2400219},
doi = {10.1109/TVLSI.2015.2400219},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YinLPLW16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YinOCLW16,
author = {Shouyi Yin and
Peng Ouyang and
Tianbao Chen and
Leibo Liu and
Shaojun Wei},
title = {A Configurable Parallel Hardware Architecture for Efficient Integral
Histogram Image Computing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {24},
number = {4},
pages = {1305--1318},
year = {2016},
url = {https://doi.org/10.1109/TVLSI.2015.2462752},
doi = {10.1109/TVLSI.2015.2462752},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YinOCLW16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YinYLLW16,
author = {Shouyi Yin and
Xianqing Yao and
Dajiang Liu and
Leibo Liu and
Shaojun Wei},
title = {Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {24},
number = {5},
pages = {1895--1908},
year = {2016},
url = {https://doi.org/10.1109/TVLSI.2015.2474129},
doi = {10.1109/TVLSI.2015.2474129},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YinYLLW16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YinZLW16,
author = {Shouyi Yin and
Pengcheng Zhou and
Leibo Liu and
Shaojun Wei},
title = {Trigger-Centric Loop Mapping on CGRAs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {24},
number = {5},
pages = {1998--2002},
year = {2016},
url = {https://doi.org/10.1109/TVLSI.2015.2486781},
doi = {10.1109/TVLSI.2015.2486781},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YinZLW16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YinXLLW16,
author = {Shouyi Yin and
Weizhi Xu and
Jiakun Li and
Leibo Liu and
Shaojun Wei},
title = {{CWFP:} Novel Collective Writeback and Fill Policy for Last-Level
{DRAM} Cache},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {24},
number = {7},
pages = {2548--2561},
year = {2016},
url = {https://doi.org/10.1109/TVLSI.2015.2507597},
doi = {10.1109/TVLSI.2015.2507597},
timestamp = {Fri, 14 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/YinXLLW16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/LinYLW16,
author = {Xinhan Lin and
Shouyi Yin and
Leibo Liu and
Shaojun Wei},
title = {Exploiting parallelism of imperfect nested loops with sibling inner
loops on coarse-grained reconfigurable architectures},
booktitle = {21st Asia and South Pacific Design Automation Conference, {ASP-DAC}
2016, Macao, Macao, January 25-28, 2016},
pages = {456--461},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ASPDAC.2016.7428054},
doi = {10.1109/ASPDAC.2016.7428054},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/LinYLW16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/YangLYW16,
author = {Chen Yang and
Leibo Liu and
Shouyi Yin and
Shaojun Wei},
title = {Data cache prefetching via context directed pattern matching for coarse-grained
reconfigurable arrays},
booktitle = {Proceedings of the 53rd Annual Design Automation Conference, {DAC}
2016, Austin, TX, USA, June 5-9, 2016},
pages = {64:1--64:6},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2897937.2898001},
doi = {10.1145/2897937.2898001},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/YangLYW16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/YinXMLW16,
author = {Shouyi Yin and
Zhicong Xie and
Chenyue Meng and
Leibo Liu and
Shaojun Wei},
editor = {Frank Liu},
title = {Multibank memory optimization for parallel data access in multiple
data arrays},
booktitle = {Proceedings of the 35th International Conference on Computer-Aided
Design, {ICCAD} 2016, Austin, TX, USA, November 7-10, 2016},
pages = {32},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2966986.2967056},
doi = {10.1145/2966986.2967056},
timestamp = {Fri, 23 Jun 2023 22:29:48 +0200},
biburl = {https://dblp.org/rec/conf/iccad/YinXMLW16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/YinYLLW16,
author = {Shouyi Yin and
Xianqing Yao and
Tianyi Lu and
Leibo Liu and
Shaojun Wei},
editor = {Frank Liu},
title = {Joint loop mapping and data placement for coarse-grained reconfigurable
architecture with multi-bank memory},
booktitle = {Proceedings of the 35th International Conference on Computer-Aided
Design, {ICCAD} 2016, Austin, TX, USA, November 7-10, 2016},
pages = {127},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2966986.2967049},
doi = {10.1145/2966986.2967049},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/YinYLLW16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nanoarch/OuyangYXLW16,
author = {Peng Ouyang and
Shouyi Yin and
Chunxiao Xing and
Leibo Liu and
Shaojun Wei},
title = {Energy management on {DVS} based coarse-grained reconfigurable platform},
booktitle = {{IEEE/ACM} International Symposium on Nanoscale Architectures, {NANOARCH}
2016, Beijing, China, July 18-20, 2016},
pages = {49--54},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2950067.2950097},
doi = {10.1145/2950067.2950097},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/nanoarch/OuyangYXLW16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/chinaf/WuDLYHW15,
author = {Chen Wu and
Chenchen Deng and
Leibo Liu and
Shouyi Yin and
Jie Han and
Shaojun Wei},
title = {Reliability-aware mapping for various NoC topologies and routing algorithms
under performance constraints},
journal = {Sci. China Inf. Sci.},
volume = {58},
number = {8},
pages = {1--14},
year = {2015},
url = {https://doi.org/10.1007/s11432-014-5248-8},
doi = {10.1007/S11432-014-5248-8},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/chinaf/WuDLYHW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/PengYLW15,
author = {Yu Peng and
Shouyi Yin and
Leibo Liu and
Shaojun Wei},
title = {Battery-Aware Loop Nests Mapping for CGRAs},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {98-D},
number = {2},
pages = {230--242},
year = {2015},
url = {https://doi.org/10.1587/transinf.2014RCP0003},
doi = {10.1587/TRANSINF.2014RCP0003},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/PengYLW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/XuYLW15,
author = {Bing Xu and
Shouyi Yin and
Leibo Liu and
Shaojun Wei},
title = {Low-Power Loop Parallelization onto {CGRA} Utilizing Variable Dual
V\({}_{\mbox{DD}}\)},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {98-D},
number = {2},
pages = {243--251},
year = {2015},
url = {https://doi.org/10.1587/transinf.2014RCP0004},
doi = {10.1587/TRANSINF.2014RCP0004},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/XuYLW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/ShiYLLLW15,
author = {Rui Shi and
Shouyi Yin and
Leibo Liu and
Qiongbing Liu and
Shuang Liang and
Shaojun Wei},
title = {The Implementation of Texture-Based Video Up-Scaling on Coarse-Grained
Reconfigurable Architecture},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {98-D},
number = {2},
pages = {276--287},
year = {2015},
url = {https://doi.org/10.1587/transinf.2014RCP0010},
doi = {10.1587/TRANSINF.2014RCP0010},
timestamp = {Thu, 22 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicet/ShiYLLLW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/LiuYLW15,
author = {Dajiang Liu and
Shouyi Yin and
Leibo Liu and
Shaojun Wei},
title = {Mapping Multi-Level Loop Nests onto CGRAs Using Polyhedral Optimizations},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {98-A},
number = {7},
pages = {1419--1430},
year = {2015},
url = {https://doi.org/10.1587/transfun.E98.A.1419},
doi = {10.1587/TRANSFUN.E98.A.1419},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/LiuYLW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcsc/YangLWYCW15,
author = {Chen Yang and
Leibo Liu and
Yansheng Wang and
Shouyi Yin and
Peng Cao and
Shaojun Wei},
title = {Configuration Approaches to Enhance Computing Efficiency of Coarse-Grained
Reconfigurable Array},
journal = {J. Circuits Syst. Comput.},
volume = {24},
number = {3},
pages = {1550043:1--1550043:21},
year = {2015},
url = {https://doi.org/10.1142/S0218126615500437},
doi = {10.1142/S0218126615500437},
timestamp = {Tue, 25 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jcsc/YangLWYCW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sensors/YinOLGW15,
author = {Shouyi Yin and
Peng Ouyang and
Leibo Liu and
Yike Guo and
Shaojun Wei},
title = {Fast Traffic Sign Recognition with a Rotation Invariant Binary Pattern
Based Feature},
journal = {Sensors},
volume = {15},
number = {1},
pages = {2161--2180},
year = {2015},
url = {https://doi.org/10.3390/s150102161},
doi = {10.3390/S150102161},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/sensors/YinOLGW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sensors/YinDJLW15,
author = {Shouyi Yin and
Hao Dong and
Guangli Jiang and
Leibo Liu and
Shaojun Wei},
title = {A Novel 2D-to-3D Video Conversion Method Using Time-Coherent Depth
Maps},
journal = {Sensors},
volume = {15},
number = {7},
pages = {15246--15264},
year = {2015},
url = {https://doi.org/10.3390/s150715246},
doi = {10.3390/S150715246},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/sensors/YinDJLW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sensors/XuYLLW15,
author = {Weizhi Xu and
Shouyi Yin and
Leibo Liu and
Zhiyong Liu and
Shaojun Wei},
title = {High-Performance Motion Estimation for Image Sensors with Video Compression},
journal = {Sensors},
volume = {15},
number = {8},
pages = {20752--20778},
year = {2015},
url = {https://doi.org/10.3390/s150820752},
doi = {10.3390/S150820752},
timestamp = {Wed, 12 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/sensors/XuYLLW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sensors/JiangLZYW15,
author = {Guangli Jiang and
Leibo Liu and
Wenping Zhu and
Shouyi Yin and
Shaojun Wei},
title = {A 181 {GOPS} {AKAZE} Accelerator Employing Discrete-Time Cellular
Neural Networks for Real-Time Feature Extraction},
journal = {Sensors},
volume = {15},
number = {9},
pages = {22509--22529},
year = {2015},
url = {https://doi.org/10.3390/s150922509},
doi = {10.3390/S150922509},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/sensors/JiangLZYW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WuDLHCYW15,
author = {Chen Wu and
Chenchen Deng and
Leibo Liu and
Jie Han and
Jiqiang Chen and
Shouyi Yin and
Shaojun Wei},
title = {An Efficient Application Mapping Approach for the Co-Optimization
of Reliability, Energy, and Performance in Reconfigurable NoC Architectures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {34},
number = {8},
pages = {1264--1277},
year = {2015},
url = {https://doi.org/10.1109/TCAD.2015.2422843},
doi = {10.1109/TCAD.2015.2422843},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WuDLHCYW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/OuyangYZLW15,
author = {Peng Ouyang and
Shouyi Yin and
Yuchi Zhang and
Leibo Liu and
Shaojun Wei},
title = {A Fast Integral Image Computing Hardware Architecture With High Power
and Area Efficiency},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {62-II},
number = {1},
pages = {75--79},
year = {2015},
url = {https://doi.org/10.1109/TCSII.2014.2362651},
doi = {10.1109/TCSII.2014.2362651},
timestamp = {Wed, 27 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/OuyangYZLW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tce/ZhangYLW15,
author = {Zhen Zhang and
Shouyi Yin and
Leibo Liu and
Shaojun Wei},
title = {A real-time time-consistent 2D-to-3D video conversion system using
color histogram},
journal = {{IEEE} Trans. Consumer Electron.},
volume = {61},
number = {4},
pages = {524--530},
year = {2015},
url = {https://doi.org/10.1109/TCE.2015.7389808},
doi = {10.1109/TCE.2015.7389808},
timestamp = {Thu, 09 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tce/ZhangYLW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tmm/LiuWZWYCYW15,
author = {Leibo Liu and
Dong Wang and
Min Zhu and
Yansheng Wang and
Shouyi Yin and
Peng Cao and
Jun Yang and
Shaojun Wei},
title = {An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit
for Multiple-Standard Video Decoding},
journal = {{IEEE} Trans. Multim.},
volume = {17},
number = {10},
pages = {1706--1720},
year = {2015},
url = {https://doi.org/10.1109/TMM.2015.2463735},
doi = {10.1109/TMM.2015.2463735},
timestamp = {Sat, 22 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tmm/LiuWZWYCYW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tmm/LiuWZWYCYW15a,
author = {Leibo Liu and
Dong Wang and
Min Zhu and
Yansheng Wang and
Shouyi Yin and
Peng Cao and
Jun Yang and
Shaojun Wei},
title = {Correction to "An Energy-Efficient Coarse-Grained Reconfigurable
Processing Unit for Multiple-Standard Video Decoding"},
journal = {{IEEE} Trans. Multim.},
volume = {17},
number = {12},
pages = {2354--2355},
year = {2015},
url = {https://doi.org/10.1109/TMM.2015.2492738},
doi = {10.1109/TMM.2015.2492738},
timestamp = {Sat, 22 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tmm/LiuWZWYCYW15a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/RenLYHW15,
author = {Yu Ren and
Leibo Liu and
Shouyi Yin and
Jie Han and
Shaojun Wei},
title = {Efficient Fault-Tolerant Topology Reconfiguration Using a Maximum
Flow Algorithm},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {8},
number = {3},
pages = {19:1--19:24},
year = {2015},
url = {https://doi.org/10.1145/2700417},
doi = {10.1145/2700417},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/RenLYHW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhuLYYW15,
author = {Jianfeng Zhu and
Leibo Liu and
Shouyi Yin and
Xiao Yang and
Shaojun Wei},
title = {A Hybrid Reconfigurable Architecture and Design Methods Aiming at
Control-Intensive Kernels},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {23},
number = {9},
pages = {1700--1709},
year = {2015},
url = {https://doi.org/10.1109/TVLSI.2014.2349652},
doi = {10.1109/TVLSI.2014.2349652},
timestamp = {Sun, 16 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhuLYYW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuWDYWHW15,
author = {Leibo Liu and
Chen Wu and
Chenchen Deng and
Shouyi Yin and
Qinghua Wu and
Jie Han and
Shaojun Wei},
title = {A Flexible Energy- and Reliability-Aware Application Mapping for NoC-Based
Reconfigurable Architectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {23},
number = {11},
pages = {2566--2580},
year = {2015},
url = {https://doi.org/10.1109/TVLSI.2014.2367108},
doi = {10.1109/TVLSI.2014.2367108},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuWDYWHW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuYPLW15,
author = {Dajiang Liu and
Shouyi Yin and
Yu Peng and
Leibo Liu and
Shaojun Wei},
title = {Optimizing Spatial Mapping of Nested Loop for Coarse-Grained Reconfigurable
Architectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {23},
number = {11},
pages = {2581--2594},
year = {2015},
url = {https://doi.org/10.1109/TVLSI.2014.2371854},
doi = {10.1109/TVLSI.2014.2371854},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuYPLW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/OuyangYLW15,
author = {Peng Ouyang and
Shouyi Yin and
Leibo Liu and
Shaojun Wei},
title = {Energy Management on Battery-Powered Coarse-Grained Reconfigurable
Platforms},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {23},
number = {12},
pages = {3085--3098},
year = {2015},
url = {https://doi.org/10.1109/TVLSI.2014.2378289},
doi = {10.1109/TVLSI.2014.2378289},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/OuyangYLW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/LiuRDYWH15,
author = {Leibo Liu and
Yu Ren and
Chenchen Deng and
Shouyi Yin and
Shaojun Wei and
Jie Han},
title = {A novel approach using a minimum cost maximum flow algorithm for fault-tolerant
topology reconfiguration in NoC architectures},
booktitle = {The 20th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2015, Chiba, Japan, January 19-22, 2015},
pages = {48--53},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ASPDAC.2015.7058980},
doi = {10.1109/ASPDAC.2015.7058980},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/LiuRDYWH15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/PengYLW15,
author = {Yu Peng and
Shouyi Yin and
Leibo Liu and
Shaojun Wei},
title = {Battery-aware mapping optimization of loop nests for CGRAs},
booktitle = {The 20th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2015, Chiba, Japan, January 19-22, 2015},
pages = {767--772},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ASPDAC.2015.7059103},
doi = {10.1109/ASPDAC.2015.7059103},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/PengYLW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/YinOLW15,
author = {Shouyi Yin and
Peng Ouyang and
Leibo Liu and
Shaojun Wei},
title = {A 83fps 1080P resolution 354 mW silicon implementation for computing
the improved robust feature in affine space},
booktitle = {2015 {IEEE} Custom Integrated Circuits Conference, {CICC} 2015, San
Jose, CA, USA, September 28-30, 2015},
pages = {1--4},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/CICC.2015.7338481},
doi = {10.1109/CICC.2015.7338481},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cicc/YinOLW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/WangLZYW15,
author = {Junbin Wang and
Leibo Liu and
Jianfeng Zhu and
Shouyi Yin and
Shaojun Wei},
title = {Acceleration of control flows on reconfigurable architecture with
a composite method},
booktitle = {Proceedings of the 52nd Annual Design Automation Conference, San Francisco,
CA, USA, June 7-11, 2015},
pages = {45:1--45:6},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2744769.2744789},
doi = {10.1145/2744769.2744789},
timestamp = {Sun, 16 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/WangLZYW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/JiangLZYW15,
author = {Guangli Jiang and
Leibo Liu and
Wenping Zhu and
Shouyi Yin and
Shaojun Wei},
title = {A 127 fps in full hd accelerator based on optimized {AKAZE} with efficiency
and effectiveness for image feature extraction},
booktitle = {Proceedings of the 52nd Annual Design Automation Conference, San Francisco,
CA, USA, June 7-11, 2015},
pages = {87:1--87:6},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2744769.2744772},
doi = {10.1145/2744769.2744772},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/JiangLZYW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/MengYOLW15,
author = {Chenyue Meng and
Shouyi Yin and
Peng Ouyang and
Leibo Liu and
Shaojun Wei},
title = {Efficient memory partitioning for parallel data access in multidimensional
arrays},
booktitle = {Proceedings of the 52nd Annual Design Automation Conference, San Francisco,
CA, USA, June 7-11, 2015},
pages = {160:1--160:6},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2744769.2744831},
doi = {10.1145/2744769.2744831},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/MengYOLW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/YinLLWG15,
author = {Shouyi Yin and
Dajiang Liu and
Leibo Liu and
Shaojun Wei and
Yike Guo},
editor = {Wolfgang Nebel and
David Atienza},
title = {Joint affine transformation and loop pipelining for mapping nested
loop on CGRAs},
booktitle = {Proceedings of the 2015 Design, Automation {\&} Test in Europe
Conference {\&} Exhibition, {DATE} 2015, Grenoble, France, March
9-13, 2015},
pages = {115--120},
publisher = {{ACM}},
year = {2015},
url = {http://dl.acm.org/citation.cfm?id=2755779},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/YinLLWG15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/YinLLWG15a,
author = {Shouyi Yin and
Jiakun Li and
Leibo Liu and
Shaojun Wei and
Yike Guo},
editor = {Wolfgang Nebel and
David Atienza},
title = {Cooperatively managing dynamic writeback and insertion policies in
a last-level {DRAM} cache},
booktitle = {Proceedings of the 2015 Design, Automation {\&} Test in Europe
Conference {\&} Exhibition, {DATE} 2015, Grenoble, France, March
9-13, 2015},
pages = {187--192},
publisher = {{ACM}},
year = {2015},
url = {http://dl.acm.org/citation.cfm?id=2755794},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/YinLLWG15a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/TuYOLW15,
author = {Fengbin Tu and
Shouyi Yin and
Peng Ouyang and
Leibo Liu and
Shaojun Wei},
editor = {Wolfgang Nebel and
David Atienza},
title = {{RNA:} a reconfigurable architecture for hardware neural acceleration},
booktitle = {Proceedings of the 2015 Design, Automation {\&} Test in Europe
Conference {\&} Exhibition, {DATE} 2015, Grenoble, France, March
9-13, 2015},
pages = {695--700},
publisher = {{ACM}},
year = {2015},
url = {http://dl.acm.org/citation.cfm?id=2755912},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/TuYOLW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/YangLYW15,
author = {Chen Yang and
Leibo Liu and
Shouyi Yin and
Shaojun Wei},
editor = {George A. Constantinides and
Deming Chen},
title = {Cost-Effective Memory Architecture to Achieve Flexible Configuration
and Efficient Data Transmission for Coarse-Grained Reconfigurable
Array (Abstract Only)},
booktitle = {Proceedings of the 2015 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, Monterey, CA, USA, February 22-24, 2015},
pages = {263},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2684746.2689103},
doi = {10.1145/2684746.2689103},
timestamp = {Tue, 06 Nov 2018 16:58:22 +0100},
biburl = {https://dblp.org/rec/conf/fpga/YangLYW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/LiuCWZYW15,
author = {Leibo Liu and
Yingjie Victor Chen and
Dong Wang and
Min Zhu and
Shouyi Yin and
Shaojun Wei},
editor = {George A. Constantinides and
Deming Chen},
title = {A Mixed-Grained Reconfigurable Computing Platform for Multiple-Standard
Video Decoding (Abstract Only)},
booktitle = {Proceedings of the 2015 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, Monterey, CA, USA, February 22-24, 2015},
pages = {267},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2684746.2689116},
doi = {10.1145/2684746.2689116},
timestamp = {Sat, 22 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/LiuCWZYW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/WangLZYW15,
author = {Junbin Wang and
Leibo Liu and
Jianfeng Zhu and
Shouyi Yin and
Shaojun Wei},
editor = {George A. Constantinides and
Deming Chen},
title = {A Novel Composite Method to Accelerate Control Flow on Reconfigurable
Architecture (Abstract Only)},
booktitle = {Proceedings of the 2015 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, Monterey, CA, USA, February 22-24, 2015},
pages = {270},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2684746.2689124},
doi = {10.1145/2684746.2689124},
timestamp = {Sun, 16 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/WangLZYW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/YinZLW15,
author = {Shouyi Yin and
Pengcheng Zhou and
Leibo Liu and
Shaojun Wei},
editor = {Diana Marculescu and
Frank Liu},
title = {Acceleration of Nested Conditionals on CGRAs via Trigger Scheme},
booktitle = {Proceedings of the {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 2015, Austin, TX, USA, November 2-6, 2015},
pages = {597--604},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ICCAD.2015.7372624},
doi = {10.1109/ICCAD.2015.7372624},
timestamp = {Mon, 26 Jun 2023 16:43:56 +0200},
biburl = {https://dblp.org/rec/conf/iccad/YinZLW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccel/DongYJLW15,
author = {Hao Dong and
Shouyi Yin and
Guangli Jiang and
Leibo Liu and
Shaojun Wei},
title = {An automatic depth map generation method by image classification},
booktitle = {{IEEE} International Conference on Consumer Electronics, {ICCE} 2015,
Las Vegas, NV, USA, January 9-12, 2015},
pages = {168--169},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ICCE.2015.7066365},
doi = {10.1109/ICCE.2015.7066365},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccel/DongYJLW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccel/ZhangYLW15,
author = {Zhen Zhang and
Shouyi Yin and
Leibo Liu and
Shaojun Wei},
title = {Real-time time-consistent 2D-to-3D video conversion based on color
histogram},
booktitle = {{IEEE} International Conference on Consumer Electronics, {ICCE} 2015,
Las Vegas, NV, USA, January 9-12, 2015},
pages = {188--189},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ICCE.2015.7066374},
doi = {10.1109/ICCE.2015.7066374},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccel/ZhangYLW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccel/TanYOLW15,
author = {Tao Tan and
Shouyi Yin and
Peng Ouyang and
Leibo Liu and
Shaojun Wei},
title = {Efficient lane detection system based on monocular camera},
booktitle = {{IEEE} International Conference on Consumer Electronics, {ICCE} 2015,
Las Vegas, NV, USA, January 9-12, 2015},
pages = {202--203},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ICCE.2015.7066381},
doi = {10.1109/ICCE.2015.7066381},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccel/TanYOLW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/TuYOLW15,
author = {Fengbin Tu and
Shouyi Yin and
Peng Ouyang and
Leibo Liu and
Shaojun Wei},
title = {Neural approximating architecture targeting multiple application domains},
booktitle = {2015 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
2015, Lisbon, Portugal, May 24-27, 2015},
pages = {2509--2512},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISCAS.2015.7169195},
doi = {10.1109/ISCAS.2015.7169195},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/TuYOLW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/wacv/DaiYOLW15,
author = {Xu Dai and
Shouyi Yin and
Peng Ouyang and
Leibo Liu and
Shaojun Wei},
title = {A Multi-modal 2D + 3D Face Recognition Method with a Novel Local Feature
Descriptor},
booktitle = {2015 {IEEE} Winter Conference on Applications of Computer Vision,
{WACV} 2015, Waikoloa, HI, USA, January 5-9, 2015},
pages = {657--662},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/WACV.2015.93},
doi = {10.1109/WACV.2015.93},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/wacv/DaiYOLW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/chinaf/CaiLYZZW14,
author = {Shanshan Cai and
Leibo Liu and
Shouyi Yin and
Renyan Zhou and
Weilong Zhang and
Shaojun Wei},
title = {Optimization of speeded-up robust feature algorithm for hardware implementation},
journal = {Sci. China Inf. Sci.},
volume = {57},
number = {4},
pages = {1--15},
year = {2014},
url = {https://doi.org/10.1007/s11432-013-4946-y},
doi = {10.1007/S11432-013-4946-Y},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/chinaf/CaiLYZZW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/chinaf/LiuCWYWWLCW14,
author = {Leibo Liu and
Yingjie Victor Chen and
Dong Wang and
Shouyi Yin and
Xing Wang and
Long Wang and
Hao Lei and
Peng Cao and
Shaojun Wei},
title = {Implementation of multi-standard video decoder on a heterogeneous
coarse-grained reconfigurable processor},
journal = {Sci. China Inf. Sci.},
volume = {57},
number = {8},
pages = {1--14},
year = {2014},
url = {https://doi.org/10.1007/s11432-013-4968-5},
doi = {10.1007/S11432-013-4968-5},
timestamp = {Sat, 22 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/chinaf/LiuCWYWWLCW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/chinaf/LiuCYZYW14,
author = {Leibo Liu and
Yingjie Victor Chen and
Shouyi Yin and
Li Zhou and
Hang Yuan and
Shaojun Wei},
title = {Implementation of {AVS} Jizhun decoder with {HW/SW} partitioning on
a coarse-grained reconfigurable multimedia system},
journal = {Sci. China Inf. Sci.},
volume = {57},
number = {8},
pages = {1--14},
year = {2014},
url = {https://doi.org/10.1007/s11432-013-4979-2},
doi = {10.1007/S11432-013-4979-2},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/chinaf/LiuCYZYW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/chinaf/LiuWYZWW14,
author = {Leibo Liu and
Yansheng Wang and
Shouyi Yin and
Min Zhu and
Xing Wang and
Shaojun Wei},
title = {Row-based configuration mechanism for a 2-D processing element array
in coarse-grained reconfigurable architecture},
journal = {Sci. China Inf. Sci.},
volume = {57},
number = {10},
pages = {1--18},
year = {2014},
url = {https://doi.org/10.1007/s11432-013-4973-8},
doi = {10.1007/S11432-013-4973-8},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/chinaf/LiuWYZWW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/chinaf/YinSLW14,
author = {Shouyi Yin and
Shengjia Shao and
Leibo Liu and
Shaojun Wei},
title = {MapReduce inspired loop mapping for coarse-grained reconfigurable
architecture},
journal = {Sci. China Inf. Sci.},
volume = {57},
number = {12},
pages = {1--14},
year = {2014},
url = {https://doi.org/10.1007/s11432-014-5198-1},
doi = {10.1007/S11432-014-5198-1},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/chinaf/YinSLW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/XuNYYW14,
author = {Ruoyu Xu and
Wai Chiu Ng and
George Jie Yuan and
Shouyi Yin and
Shaojun Wei},
title = {A 1/2.5 inch {VGA} 400 fps {CMOS} Image Sensor With High Sensitivity
for Machine Vision},
journal = {{IEEE} J. Solid State Circuits},
volume = {49},
number = {10},
pages = {2342--2351},
year = {2014},
url = {https://doi.org/10.1109/JSSC.2014.2345018},
doi = {10.1109/JSSC.2014.2345018},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/XuNYYW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sensors/YinDOLW14,
author = {Shouyi Yin and
Xu Dai and
Peng Ouyang and
Leibo Liu and
Shaojun Wei},
title = {A Multi-Modal Face Recognition Method Using Complete Local Derivative
Patterns and Depth Maps},
journal = {Sensors},
volume = {14},
number = {10},
pages = {19561--19581},
year = {2014},
url = {https://doi.org/10.3390/s141019561},
doi = {10.3390/S141019561},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/sensors/YinDOLW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tce/LiuZYTP14,
author = {Leibo Liu and
Wenping Zhu and
Shouyi Yin and
Eugene Tang and
Paul Peng},
title = {An uneven-dual-core processor based mobile platform for facilitating
the collaboration among various embedded electronic devices},
journal = {{IEEE} Trans. Consumer Electron.},
volume = {60},
number = {1},
pages = {137--145},
year = {2014},
url = {https://doi.org/10.1109/TCE.2014.6780936},
doi = {10.1109/TCE.2014.6780936},
timestamp = {Thu, 09 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tce/LiuZYTP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangLYZCYW14,
author = {Yansheng Wang and
Leibo Liu and
Shouyi Yin and
Min Zhu and
Peng Cao and
Jun Yang and
Shaojun Wei},
title = {On-Chip Memory Hierarchy in One Coarse-Grained Reconfigurable Architecture
to Compress Memory Space and to Reduce Reconfiguration Time and Data-Reference
Time},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {22},
number = {5},
pages = {983--994},
year = {2014},
url = {https://doi.org/10.1109/TVLSI.2013.2263155},
doi = {10.1109/TVLSI.2013.2263155},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangLYZCYW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuWYCZW14,
author = {Leibo Liu and
Dong Wang and
Shouyi Yin and
Yingjie Victor Chen and
Min Zhu and
Shaojun Wei},
title = {SimRPU: {A} Simulation Environment for Reconfigurable Architecture
Exploration},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {22},
number = {12},
pages = {2635--2648},
year = {2014},
url = {https://doi.org/10.1109/TVLSI.2013.2295622},
doi = {10.1109/TVLSI.2013.2295622},
timestamp = {Sat, 22 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuWYCZW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/YinOLW14,
author = {Shouyi Yin and
Peng Ouyang and
Leibo Liu and
Shaojun Wei},
editor = {Gerhard P. Fettweis and
Wolfgang Nebel},
title = {Extending lifetime of battery-powered coarse-grained reconfigurable
computing platforms},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2014, Dresden, Germany, March 24-28, 2014},
pages = {1--6},
publisher = {European Design and Automation Association},
year = {2014},
url = {https://doi.org/10.7873/DATE.2014.350},
doi = {10.7873/DATE.2014.350},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/YinOLW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/LiuYLW14,
author = {Dajiang Liu and
Shouyi Yin and
Leibo Liu and
Shaojun Wei},
title = {Exploiting Outer Loop Parallelism of Nested Loop on Coarse-Grained
Reconfigurable Architectures},
booktitle = {22nd {IEEE} Annual International Symposium on Field-Programmable Custom
Computing Machines, {FCCM} 2014, Boston, MA, USA, May 11-13, 2014},
pages = {32},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/FCCM.2014.19},
doi = {10.1109/FCCM.2014.19},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/LiuYLW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fie/DengLLYW14,
author = {Chenchen Deng and
Leibo Liu and
Zhaoshi Li and
Shouyi Yin and
Shaojun Wei},
title = {Teach Reconfigurable Computing using mixed-grained fabrics based hardware
infrastructure},
booktitle = {{IEEE} Frontiers in Education Conference, {FIE} 2014, Proceedings,
Madrid, Spain, October 22-25, 2014},
pages = {1--9},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/FIE.2014.7044092},
doi = {10.1109/FIE.2014.7044092},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fie/DengLLYW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/YangLWYCW14,
author = {Chen Yang and
Leibo Liu and
Yansheng Wang and
Shouyi Yin and
Peng Cao and
Shaojun Wei},
title = {Configuration approaches to improve computing efficiency of coarse-grained
reconfigurable multimedia processor},
booktitle = {24th International Conference on Field Programmable Logic and Applications,
{FPL} 2014, Munich, Germany, 2-4 September, 2014},
pages = {1--4},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/FPL.2014.6927439},
doi = {10.1109/FPL.2014.6927439},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/YangLWYCW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icpr/OuyangYLW14,
author = {Peng Ouyang and
Shouyi Yin and
Leibo Liu and
Shaojun Wei},
title = {A {FAST} Extreme Illumination Robust Feature in Affine Space},
booktitle = {22nd International Conference on Pattern Recognition, {ICPR} 2014,
Stockholm, Sweden, August 24-28, 2014},
pages = {2365--2370},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/ICPR.2014.410},
doi = {10.1109/ICPR.2014.410},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icpr/OuyangYLW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ShaoYLW14,
author = {Shengjia Shao and
Shouyi Yin and
Leibo Liu and
Shaojun Wei},
title = {Map-reduce inspired loop parallelization on {CGRA}},
booktitle = {{IEEE} International Symposium on Circuits and Systemss, {ISCAS} 2014,
Melbourne, Victoria, Australia, June 1-5, 2014},
pages = {1231--1234},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISCAS.2014.6865364},
doi = {10.1109/ISCAS.2014.6865364},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/ShaoYLW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ZhangYOLW14,
author = {Yuchi Zhang and
Shouyi Yin and
Peng Ouyang and
Leibo Liu and
Shaojun Wei},
title = {A parallel hardware architecture for fast integral image computing},
booktitle = {{IEEE} International Symposium on Circuits and Systemss, {ISCAS} 2014,
Melbourne, Victoria, Australia, June 1-5, 2014},
pages = {2189--2192},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISCAS.2014.6865603},
doi = {10.1109/ISCAS.2014.6865603},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/ZhangYOLW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ZhuLYDWTSP14,
author = {Wenping Zhu and
Leibo Liu and
Shouyi Yin and
Yuan Dong and
Shaojun Wei and
Eugene Y. Tang and
Jiqiang Song and
Jinzhan Peng},
title = {A 65 nm uneven-dual-core SoC based platform for multi-device collaborative
computing},
booktitle = {{IEEE} International Symposium on Circuits and Systemss, {ISCAS} 2014,
Melbourne, Victoria, Australia, June 1-5, 2014},
pages = {2527--2530},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISCAS.2014.6865687},
doi = {10.1109/ISCAS.2014.6865687},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/ZhuLYDWTSP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/XuYLW14,
author = {Bing Xu and
Shouyi Yin and
Leibo Liu and
Shaojun Wei},
title = {Low-power loop pipelining mapping onto {CGRA} utilizing variable dual
{VDD}},
booktitle = {{IEEE} 57th International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2014, College Station, TX, USA, August 3-6, 2014},
pages = {242--245},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/MWSCAS.2014.6908397},
doi = {10.1109/MWSCAS.2014.6908397},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mwscas/XuYLW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/robio/YinOLW14,
author = {Shouyi Yin and
Peng Ouyang and
Leibo Liu and
Shaojun Wei},
title = {A fast and robust traffic sign recognition method using ring of {RIBP}
histograms based feature},
booktitle = {2014 {IEEE} International Conference on Robotics and Biomimetics,
{ROBIO} 2014, Bali, Indonesia, December 5-10, 2014},
pages = {2570--2575},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ROBIO.2014.7090728},
doi = {10.1109/ROBIO.2014.7090728},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/robio/YinOLW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/chinaf/LiuJYWSTW13,
author = {Leibo Liu and
Wen Jia and
Shouyi Yin and
Dong Wang and
Guanyi Sun and
Eugene Tang and
Shaojun Wei},
title = {ReSSIM: a mixed-level simulator for dynamic coarse-grained reconfigurable
processor},
journal = {Sci. China Inf. Sci.},
volume = {56},
number = {6},
pages = {1--16},
year = {2013},
url = {https://doi.org/10.1007/s11432-013-4812-y},
doi = {10.1007/S11432-013-4812-Y},
timestamp = {Sat, 22 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/chinaf/LiuJYWSTW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/chinaf/ZhangLYZCW13,
author = {Weilong Zhang and
Leibo Liu and
Shouyi Yin and
Renyan Zhou and
Shanshan Cai and
Shaojun Wei},
title = {An efficient {VLSI} architecture of speeded-up robust feature extraction
for high resolution and high frame rate video},
journal = {Sci. China Inf. Sci.},
volume = {56},
number = {7},
pages = {1--14},
year = {2013},
url = {https://doi.org/10.1007/s11432-013-4786-9},
doi = {10.1007/S11432-013-4786-9},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/chinaf/ZhangLYZCW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/chinaf/WangLYZCYW13,
author = {Yansheng Wang and
Leibo Liu and
Shouyi Yin and
Min Zhu and
Peng Cao and
Jun Yang and
Shaojun Wei},
title = {Hierarchical representation of on-chip context to reduce reconfiguration
time and implementation area for coarse-grained reconfigurable architecture},
journal = {Sci. China Inf. Sci.},
volume = {56},
number = {11},
pages = {1--20},
year = {2013},
url = {https://doi.org/10.1007/s11432-013-4842-5},
doi = {10.1007/S11432-013-4842-5},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/chinaf/WangLYZCYW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/ZhangYOLW13,
author = {Jienan Zhang and
Shouyi Yin and
Peng Ouyang and
Leibo Liu and
Shaojun Wei},
title = {Concurrent Detection and Recognition of Individual Object Based on
Colour and p-SIFT Features},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {96-A},
number = {6},
pages = {1357--1365},
year = {2013},
url = {https://doi.org/10.1587/transfun.E96.A.1357},
doi = {10.1587/TRANSFUN.E96.A.1357},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/ZhangYOLW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/OuyangYGLW13,
author = {Peng Ouyang and
Shouyi Yin and
Hui Gao and
Leibo Liu and
Shaojun Wei},
title = {Parallelization of Computing-Intensive Tasks of {SIFT} Algorithm on
a Reconfigurable Architecture System},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {96-A},
number = {6},
pages = {1393--1402},
year = {2013},
url = {https://doi.org/10.1587/transfun.E96.A.1393},
doi = {10.1587/TRANSFUN.E96.A.1393},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/OuyangYGLW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/YinLLW13,
author = {Shouyi Yin and
Dajiang Liu and
Leibo Liu and
Shaojun Wei},
title = {Affine Transformations for Communication and Reconfiguration Optimization
of Mapping Loop Nests on CGRAs},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {96-D},
number = {8},
pages = {1582--1591},
year = {2013},
url = {https://doi.org/10.1587/transinf.E96.D.1582},
doi = {10.1587/TRANSINF.E96.D.1582},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/YinLLW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/WangLYZCYW13,
author = {Yansheng Wang and
Leibo Liu and
Shouyi Yin and
Min Zhu and
Peng Cao and
Jun Yang and
Shaojun Wei},
title = {The Organization of On-Chip Data Memory in One Coarse-Grained Reconfigurable
Architecture},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {96-A},
number = {11},
pages = {2218--2229},
year = {2013},
url = {https://doi.org/10.1587/transfun.E96.A.2218},
doi = {10.1587/TRANSFUN.E96.A.2218},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/WangLYZCYW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/YinSLW13,
author = {Shouyi Yin and
Rui Shi and
Leibo Liu and
Shaojun Wei},
title = {Battery-Aware Task Mapping for Coarse-Grained Reconfigurable Architecture},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {96-D},
number = {12},
pages = {2524--2535},
year = {2013},
url = {https://doi.org/10.1587/transinf.E96.D.2524},
doi = {10.1587/TRANSINF.E96.D.2524},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/YinSLW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/ZhangYLW13,
author = {Zhen Zhang and
Shouyi Yin and
Leibo Liu and
Shaojun Wei},
title = {An Inductive-Coupling Interconnected Application-Specific 3D NoC Design},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {96-A},
number = {12},
pages = {2633--2644},
year = {2013},
url = {https://doi.org/10.1587/transfun.E96.A.2633},
doi = {10.1587/TRANSFUN.E96.A.2633},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/ZhangYLW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijdsn/YinCLW13,
author = {Shouyi Yin and
Jianwei Cui and
Leibo Liu and
Shaojun Wei},
title = {Calibration Techniques for Low-Power Wireless Multiband Transceiver},
journal = {Int. J. Distributed Sens. Networks},
volume = {9},
year = {2013},
url = {https://doi.org/10.1155/2013/754206},
doi = {10.1155/2013/754206},
timestamp = {Sun, 21 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijdsn/YinCLW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/RenLYHWW13,
author = {Yu Ren and
Leibo Liu and
Shouyi Yin and
Jie Han and
Qinghua Wu and
Shaojun Wei},
title = {A fault tolerant NoC architecture using quad-spare mesh topology and
dynamic reconfiguration},
journal = {J. Syst. Archit.},
volume = {59},
number = {7},
pages = {482--491},
year = {2013},
url = {https://doi.org/10.1016/j.sysarc.2013.03.010},
doi = {10.1016/J.SYSARC.2013.03.010},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/RenLYHWW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sensors/XiaYO13,
author = {Wei Xia and
Shouyi Yin and
Peng Ouyang},
title = {A High Precision Feature Based on {LBP} and Gabor Theory for Face
Recognition},
journal = {Sensors},
volume = {13},
number = {4},
pages = {4499--4513},
year = {2013},
url = {https://doi.org/10.3390/s130404499},
doi = {10.3390/S130404499},
timestamp = {Wed, 14 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/sensors/XiaYO13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/ZhuLYW13,
author = {Jianfeng Zhu and
Leibo Liu and
Shouyi Yin and
Shaojun Wei},
title = {Low-Power Reconfigurable Processor Utilizing Variable Dual V\({}_{\mbox{DD}}\)},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {60-II},
number = {4},
pages = {217--221},
year = {2013},
url = {https://doi.org/10.1109/TCSII.2013.2251940},
doi = {10.1109/TCSII.2013.2251940},
timestamp = {Sun, 16 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/ZhuLYW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/LiuDWZYCW13,
author = {Leibo Liu and
Chenchen Deng and
Dong Wang and
Min Zhu and
Shouyi Yin and
Peng Cao and
Shaojun Wei},
title = {An energy-efficient coarse-grained dynamically reconfigurable fabric
for multiple-standard video decoding applications},
booktitle = {Proceedings of the {IEEE} 2013 Custom Integrated Circuits Conference,
{CICC} 2013, San Jose, CA, USA, September 22-25, 2013},
pages = {1--4},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/CICC.2013.6658434},
doi = {10.1109/CICC.2013.6658434},
timestamp = {Sat, 22 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cicc/LiuDWZYCW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/LiuZDYCW13,
author = {Leibo Liu and
Weilong Zhang and
Chenchen Deng and
Shouyi Yin and
Shanshan Cai and
Shaojun Wei},
title = {{SURFEX:} {A} 57fps 1080P resolution 220mW silicon implementation
for simplified speeded-up robust feature with 65nm process},
booktitle = {Proceedings of the {IEEE} 2013 Custom Integrated Circuits Conference,
{CICC} 2013, San Jose, CA, USA, September 22-25, 2013},
pages = {1--4},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/CICC.2013.6658435},
doi = {10.1109/CICC.2013.6658435},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cicc/LiuZDYCW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/LiuYLW13,
author = {Dajiang Liu and
Shouyi Yin and
Leibo Liu and
Shaojun Wei},
title = {Polyhedral model based mapping optimization of loop nests for CGRAs},
booktitle = {The 50th Annual Design Automation Conference 2013, {DAC} '13, Austin,
TX, USA, May 29 - June 07, 2013},
pages = {19:1--19:8},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2463209.2488757},
doi = {10.1145/2463209.2488757},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/LiuYLW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/emc/LiLYMW13,
author = {Guoyong Li and
Leibo Liu and
Shouyi Yin and
Changkui Mao and
Shaojun Wei},
editor = {Yueh{-}Min Huang and
Han{-}Chieh Chao and
Der{-}Jiunn Deng and
James J. Park},
title = {Mapping {IDCT} of {MPEG2} on Coarse-Grained Reconfigurable Array for
Matching 1080p Video Decoding},
booktitle = {Advanced Technologies, Embedded and Multimedia for Human-centric Computing
- HumanCom and {EMC} 2013 [International Conference on Human-centric
Computing, HumanCom 2013 / 8th International Conference on Embedded
and Multimedia Computing, {EMC} 2013, Taipei, Taiwan, August 23-25,
2013]},
series = {Lecture Notes in Electrical Engineering},
volume = {260},
pages = {545--555},
publisher = {Springer},
year = {2013},
url = {https://doi.org/10.1007/978-94-007-7262-5\_62},
doi = {10.1007/978-94-007-7262-5\_62},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/emc/LiLYMW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ZhangYLW13,
author = {Zhen Zhang and
Shouyi Yin and
Leibo Liu and
Shaojun Wei},
title = {An inductive-coupling interconnected application-specific 3D NoC design},
booktitle = {2013 {IEEE} International Symposium on Circuits and Systems (ISCAS2013),
Beijing, China, May 19-23, 2013},
pages = {550--553},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ISCAS.2013.6571902},
doi = {10.1109/ISCAS.2013.6571902},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/ZhangYLW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/LiuCYWWWZLC13,
author = {Leibo Liu and
Yingjie Victor Chen and
Shouyi Yin and
Dong Wang and
Xing Wang and
Shaojun Wei and
Li Zhou and
Hao Lei and
Peng Cao},
title = {Implementation of multi-standard video decoding algorithms on a coarse-grained
reconfigurable multimedia processor},
booktitle = {2013 {IEEE} International Symposium on Circuits and Systems (ISCAS2013),
Beijing, China, May 19-23, 2013},
pages = {897--900},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ISCAS.2013.6571992},
doi = {10.1109/ISCAS.2013.6571992},
timestamp = {Sat, 22 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/LiuCYWWWZLC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/RenLYWWH13,
author = {Yu Ren and
Leibo Liu and
Shouyi Yin and
Qinghua Wu and
Shaojun Wei and
Jie Han},
title = {A {VLSI} architecture for enhancing the fault tolerance of NoC using
quad-spare mesh topology and dynamic reconfiguration},
booktitle = {2013 {IEEE} International Symposium on Circuits and Systems (ISCAS2013),
Beijing, China, May 19-23, 2013},
pages = {1793--1796},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ISCAS.2013.6572213},
doi = {10.1109/ISCAS.2013.6572213},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/RenLYWWH13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/LiuYLW13,
author = {Dajiang Liu and
Shouyi Yin and
Leibo Liu and
Shaojun Wei},
title = {Affine transformations for communication and reconfiguration optimization
of loops on CGRAs},
booktitle = {2013 {IEEE} International Symposium on Circuits and Systems (ISCAS2013),
Beijing, China, May 19-23, 2013},
pages = {2541--2544},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ISCAS.2013.6572396},
doi = {10.1109/ISCAS.2013.6572396},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/LiuYLW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nas/WuLYRW13,
author = {Qinghua Wu and
Leibo Liu and
Shouyi Yin and
Yu Ren and
Shaojun Wei},
title = {{SPC:} An Approach to Guarantee Performance in Cost Oriented Mapping
Algorithm for NoC Architectures},
booktitle = {{IEEE} Eighth International Conference on Networking, Architecture
and Storage, {NAS} 2013, Xi'an, Shaanxi, China, July 17-19, 2013},
pages = {187--190},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/NAS.2013.30},
doi = {10.1109/NAS.2013.30},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/nas/WuLYRW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nas/LiYLWW13,
author = {Yulin Li and
Shouyi Yin and
Leibo Liu and
Shaojun Wei and
Dong Wang},
title = {Battery-Aware {MAC} Analytical Modeling for Extending Lifetime of
Low Duty-Cycled Wireless Sensor Network},
booktitle = {{IEEE} Eighth International Conference on Networking, Architecture
and Storage, {NAS} 2013, Xi'an, Shaanxi, China, July 17-19, 2013},
pages = {297--301},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/NAS.2013.47},
doi = {10.1109/NAS.2013.47},
timestamp = {Sat, 22 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/nas/LiYLWW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/YinYLZW12,
author = {Shouyi Yin and
Chongyong Yin and
Leibo Liu and
Min Zhu and
Shaojun Wei},
title = {Configuration Context Reduction for Coarse-Grained Reconfigurable
Architecture},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {95-D},
number = {2},
pages = {335--344},
year = {2012},
url = {https://doi.org/10.1587/transinf.E95.D.335},
doi = {10.1587/TRANSINF.E95.D.335},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/YinYLZW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/YinHZLW12,
author = {Shouyi Yin and
Yang Hu and
Zhen Zhang and
Leibo Liu and
Shaojun Wei},
title = {Hybrid Wired/Wireless On-Chip Network Design for Application-Specific
SoC},
journal = {{IEICE} Trans. Electron.},
volume = {95-C},
number = {4},
pages = {495--505},
year = {2012},
url = {https://doi.org/10.1587/transele.E95.C.495},
doi = {10.1587/TRANSELE.E95.C.495},
timestamp = {Sun, 24 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/YinHZLW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/OuyangYLW12,
author = {Peng Ouyang and
Shouyi Yin and
Leibo Liu and
Shaojun Wei},
title = {Multi-Battery Scheduling for Battery-Powered {DVS} Systems},
journal = {{IEICE} Trans. Commun.},
volume = {95-B},
number = {7},
pages = {2278--2285},
year = {2012},
url = {https://doi.org/10.1587/transcom.E95.B.2278},
doi = {10.1587/TRANSCOM.E95.B.2278},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/OuyangYLW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/LiuYYLW12,
author = {Dajiang Liu and
Shouyi Yin and
Chongyong Yin and
Leibo Liu and
Shaojun Wei},
title = {Mapping Optimization of Affine Loop Nests for Reconfigurable Computing
Architecture},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {95-D},
number = {12},
pages = {2898--2907},
year = {2012},
url = {https://doi.org/10.1587/transinf.E95.D.2898},
doi = {10.1587/TRANSINF.E95.D.2898},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/LiuYYLW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/YinYLZWW12,
author = {Shouyi Yin and
Chongyong Yin and
Leibo Liu and
Min Zhu and
Yansheng Wang and
Shaojun Wei},
title = {Reducing configuration contexts for coarse-grained reconfigurable
architecture},
booktitle = {2012 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
2012, Seoul, Korea (South), May 20-23, 2012},
pages = {121--124},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISCAS.2012.6271452},
doi = {10.1109/ISCAS.2012.6271452},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/YinYLZWW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asicon/YinCLLW11,
author = {Shouyi Yin and
Jianwei Cui and
Ao Luo and
Leibo Liu and
Shaojun Wei},
title = {A high efficient baseband transceiver for {IEEE} 802.15.4 {LR-WPAN}
systems},
booktitle = {2011 {IEEE} 9th International Conference on ASIC, {ASICON} 2011, Xiamen,
China, October 25-28, 2011},
pages = {224--227},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ASICON.2011.6157162},
doi = {10.1109/ASICON.2011.6157162},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asicon/YinCLLW11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asicon/LiangYYLW11,
author = {Shuang Liang and
Shouyi Yin and
Chongyong Yin and
Leibo Liu and
Shaojun Wei},
title = {Performance evaluation modeling for reconfigurable processor},
booktitle = {2011 {IEEE} 9th International Conference on ASIC, {ASICON} 2011, Xiamen,
China, October 25-28, 2011},
pages = {570--573},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ASICON.2011.6157269},
doi = {10.1109/ASICON.2011.6157269},
timestamp = {Thu, 22 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asicon/LiangYYLW11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/YinSLW10,
author = {Shouyi Yin and
Zhongfu Sun and
Leibo Liu and
Shaojun Wei},
title = {CropNET: {A} Wireless Multimedia Sensor Network for Agricultural Monitoring},
journal = {{IEICE} Trans. Commun.},
volume = {93-B},
number = {8},
pages = {2073--2076},
year = {2010},
url = {https://doi.org/10.1587/transcom.E93.B.2073},
doi = {10.1587/TRANSCOM.E93.B.2073},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/YinSLW10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/ZhuLYYW10,
author = {Min Zhu and
Leibo Liu and
Shouyi Yin and
Chongyong Yin and
Shaojun Wei},
title = {A Cycle-Accurate Simulator for a Reconfigurable Multi-Media System},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {93-D},
number = {12},
pages = {3202--3210},
year = {2010},
url = {https://doi.org/10.1587/transinf.E93.D.3202},
doi = {10.1587/TRANSINF.E93.D.3202},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/ZhuLYYW10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/GengLYZW10,
author = {Tongsheng Geng and
Leibo Liu and
Shouyi Yin and
Min Zhu and
Shaojun Wei},
title = {Parallelization of Computing-Intensive Tasks of the {H.264} High Profile
Decoding Algorithm on a Reconfigurable Multimedia System},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {93-D},
number = {12},
pages = {3223--3231},
year = {2010},
url = {https://doi.org/10.1587/transinf.E93.D.3223},
doi = {10.1587/TRANSINF.E93.D.3223},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/GengLYZW10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/OuyangYLW10,
author = {Peng Ouyang and
Shouyi Yin and
Leibo Liu and
Shaojun Wei},
title = {Battery aware tasks allocating algorithm for multi-battery operated
system},
booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS} 2010,
Kuala Lumpur, Malaysia, December 6-9, 2010},
pages = {875--878},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/APCCAS.2010.5774998},
doi = {10.1109/APCCAS.2010.5774998},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/apccas/OuyangYLW10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/HuYLW10,
author = {Yang Hu and
Shouyi Yin and
Leibo Liu and
Shaojun Wei},
title = {Mixed-level modeling for network on chip infrastructure in SoC design},
booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS} 2010,
Kuala Lumpur, Malaysia, December 6-9, 2010},
pages = {911--914},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/APCCAS.2010.5774752},
doi = {10.1109/APCCAS.2010.5774752},
timestamp = {Sun, 24 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/apccas/HuYLW10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/bibm/YinLWJ10,
author = {Shouyi Yin and
Tao Liu and
Huafeng Wei and
Guang Ji},
title = {Syndrome differentiation of fatty liver based on the whole network
analysis theory},
booktitle = {2010 {IEEE} International Conference on Bioinformatics and Biomedicine
Workshops, {BIBMW} 2010, Hong Kong, December 18, 2010},
pages = {598--602},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/BIBMW.2010.5703868},
doi = {10.1109/BIBMW.2010.5703868},
timestamp = {Wed, 24 Nov 2021 15:06:06 +0100},
biburl = {https://dblp.org/rec/conf/bibm/YinLWJ10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ZhouLYLCW10,
author = {Renyan Zhou and
Leibo Liu and
Shouyi Yin and
Ao Luo and
Xinkai Chen and
Shaojun Wei},
title = {A {VLSI} design of sensor node for wireless image sensor network},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2010), May
30 - June 2, 2010, Paris, France},
pages = {149--152},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ISCAS.2010.5538037},
doi = {10.1109/ISCAS.2010.5538037},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/ZhouLYLCW10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/GengLYZJW10,
author = {Tongsheng Geng and
Leibo Liu and
Shouyi Yin and
Min Zhu and
Wen Jia and
Shaojun Wei},
title = {Parallel implementation of computing-intensive decoding algorithms
of {H.264} on reconfigurable SoC},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2010), May
30 - June 2, 2010, Paris, France},
pages = {1153--1156},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ISCAS.2010.5537314},
doi = {10.1109/ISCAS.2010.5537314},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/GengLYZJW10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ZhuLYWWW10,
author = {Min Zhu and
Leibo Liu and
Shouyi Yin and
Yansheng Wang and
Wenjie Wang and
Shaojun Wei},
title = {A reconfigurable multi-processor SoC for media applications},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2010), May
30 - June 2, 2010, Paris, France},
pages = {2011--2014},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ISCAS.2010.5537147},
doi = {10.1109/ISCAS.2010.5537147},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/ZhuLYWWW10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/chinaf/YinLW09,
author = {Shouyi Yin and
Leibo Liu and
Shaojun Wei},
title = {Buffer planning for application-specific networks-on-chip design},
journal = {Sci. China Ser. {F} Inf. Sci.},
volume = {52},
number = {4},
pages = {547--558},
year = {2009},
url = {https://doi.org/10.1007/s11432-009-0085-x},
doi = {10.1007/S11432-009-0085-X},
timestamp = {Mon, 18 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/chinaf/YinLW09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/YinYLW09,
author = {Chongyong Yin and
Shouyi Yin and
Leibo Liu and
Shaojun Wei},
title = {Compiler Framework for Reconfigurable Computing Architecture},
journal = {{IEICE} Trans. Electron.},
volume = {92-C},
number = {10},
pages = {1284--1290},
year = {2009},
url = {https://doi.org/10.1587/transele.E92.C.1284},
doi = {10.1587/TRANSELE.E92.C.1284},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/YinYLW09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/wicomm/YinXZL06,
author = {Shouyi Yin and
Yongqiang Xiong and
Qian Zhang and
Xiaokang Lin},
title = {Traffic-aware routing for real-time communications in wireless multi-hop
networks},
journal = {Wirel. Commun. Mob. Comput.},
volume = {6},
pages = {825--843},
year = {2006},
url = {https://doi.org/10.1002/wcm.444},
doi = {10.1002/WCM.444},
timestamp = {Thu, 06 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/wicomm/YinXZL06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/qshine/YinXZL06,
author = {Shouyi Yin and
Yongqiang Xiong and
Qian Zhang and
Xiaokang Lin},
editor = {Jon W. Mark},
title = {Prediction-based routing for real time communications in wireless
multi-hop networks},
booktitle = {3rd International {ICST} Conference on Quality of Service in Heterogeneous
Wired/Wireless Networks, {QSHINE} 2006, Waterloo, Canada, August 7-9,
2006},
pages = {28},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1185373.1185409},
doi = {10.1145/1185373.1185409},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/qshine/YinXZL06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sutc/YinXLZ06,
author = {Shouyi Yin and
Yongqiang Xiong and
Xiaokang Lin and
Qian Zhang},
title = {Traffic-aware Routing for Real Time Communications in Wireless Multi-hop
Networks},
booktitle = {{IEEE} International Conference on Sensor Networks, Ubiquitous, and
Trustworthy Computing {(SUTC} 2006), 5-7 June 2006, Taichung, Taiwan},
pages = {568--569},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.ieeecomputersociety.org/10.1109/SUTC.2006.137},
doi = {10.1109/SUTC.2006.137},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/sutc/YinXLZ06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icc/YinL05,
author = {Shouyi Yin and
Xiaokang Lin},
title = {Multipath minimum energy routing in ad hoc network},
booktitle = {Proceedings of {IEEE} International Conference on Communications,
{ICC} 2005, Seoul, Korea, 16-20 May 2005},
pages = {3182--3186},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/ICC.2005.1495003},
doi = {10.1109/ICC.2005.1495003},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/icc/YinL05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icn/YinL05,
author = {Shouyi Yin and
Xiaokang Lin},
editor = {Pascal Lorenz and
Petre Dini},
title = {Multipath Energy Efficient Routing in Mobile Ad Hoc Network},
booktitle = {Networking - {ICN} 2005, 4th International Conference on Networking,
ReunionIsland, France, April 17-21, 2005, Proceedings, Part {II}},
series = {Lecture Notes in Computer Science},
volume = {3421},
pages = {226--233},
publisher = {Springer},
year = {2005},
url = {https://doi.org/10.1007/978-3-540-31957-3\_28},
doi = {10.1007/978-3-540-31957-3\_28},
timestamp = {Tue, 14 May 2019 10:00:47 +0200},
biburl = {https://dblp.org/rec/conf/icn/YinL05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/wcnc/YinL05,
author = {Shouyi Yin and
Xiaokang Lin},
title = {Adaptive load balancing in mobile ad hoc networks},
booktitle = {{IEEE} Wireless Communications and Networking Conference, {WCNC} 2005,
March 13-17, 2005, New Orleans, Louisiana, {USA}},
pages = {1982--1987},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/WCNC.2005.1424823},
doi = {10.1109/WCNC.2005.1424823},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/wcnc/YinL05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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