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BibTeX records: Tomokazu Yoneda
@article{DBLP:journals/ieicet/HossainYI17, author = {Fakir Sharif Hossain and Tomokazu Yoneda and Michiko Inoue}, title = {An Effective and Sensitive Scan Segmentation Technique for Detecting Hardware Trojan}, journal = {{IEICE} Trans. Inf. Syst.}, volume = {100-D}, number = {1}, pages = {130--139}, year = {2017}, url = {https://doi.org/10.1587/transinf.2016EDP7246}, doi = {10.1587/TRANSINF.2016EDP7246}, timestamp = {Sat, 11 Apr 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/ieicet/HossainYI17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/integration/NaeiniDOYI17, author = {Mahshid Mojtabavi Naeini and Sreedharan Baskara Dass and Chia Yee Ooi and Tomokazu Yoneda and Michiko Inoue}, title = {An integrated {DFT} solution for power reduction in scan test applications by low power gating scan cell}, journal = {Integr.}, volume = {57}, pages = {108--124}, year = {2017}, url = {https://doi.org/10.1016/j.vlsi.2016.12.009}, doi = {10.1016/J.VLSI.2016.12.009}, timestamp = {Thu, 20 Feb 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/integration/NaeiniDOYI17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ats/HossainYSIO17, author = {Fakir Sharif Hossain and Tomokazu Yoneda and Michihiro Shintani and Michiko Inoue and Alex Orailoglu}, title = {Intra-Die-Variation-Aware Side Channel Analysis for Hardware Trojan Detection}, booktitle = {26th {IEEE} Asian Test Symposium, {ATS} 2017, Taipei City, Taiwan, November 27-30, 2017}, pages = {52--57}, publisher = {{IEEE} Computer Society}, year = {2017}, url = {https://doi.org/10.1109/ATS.2017.22}, doi = {10.1109/ATS.2017.22}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/ats/HossainYSIO17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ets/HossainYIO17, author = {Fakir Sharif Hossain and Tomokazu Yoneda and Michiko Inoue and Alex Orailoglu}, title = {Detecting hardware Trojans without a Golden {IC} through clock-tree defined circuit partitions}, booktitle = {22nd {IEEE} European Test Symposium, {ETS} 2017, Limassol, Cyprus, May 22-26, 2017}, pages = {1--6}, publisher = {{IEEE}}, year = {2017}, url = {https://doi.org/10.1109/ETS.2017.7968246}, doi = {10.1109/ETS.2017.7968246}, timestamp = {Wed, 16 Oct 2019 14:14:53 +0200}, biburl = {https://dblp.org/rec/conf/ets/HossainYIO17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/ieicet/MayugaYYSI16, author = {Gian Mayuga and Yuta Yamato and Tomokazu Yoneda and Yasuo Sato and Michiko Inoue}, title = {Reliability-Enhanced ECC-Based Memory Architecture Using In-Field Self-Repair}, journal = {{IEICE} Trans. Inf. Syst.}, volume = {99-D}, number = {10}, pages = {2591--2599}, year = {2016}, url = {https://doi.org/10.1587/transinf.2015EDP7408}, doi = {10.1587/TRANSINF.2015EDP7408}, timestamp = {Sat, 11 Apr 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/ieicet/MayugaYYSI16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ets/MayugaYYSI16, author = {Gian Mayuga and Yuta Yamato and Tomokazu Yoneda and Yasuo Sato and Michiko Inoue}, title = {Reliability enhancement of embedded memory with combination of aging-aware adaptive in-field self-repair and {ECC}}, booktitle = {21th {IEEE} European Test Symposium, {ETS} 2016, Amsterdam, Netherlands, May 23-27, 2016}, pages = {1--2}, publisher = {{IEEE}}, year = {2016}, url = {https://doi.org/10.1109/ETS.2016.7519284}, doi = {10.1109/ETS.2016.7519284}, timestamp = {Wed, 16 Oct 2019 14:14:53 +0200}, biburl = {https://dblp.org/rec/conf/ets/MayugaYYSI16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ets/MayugaYYIS15, author = {Gian Mayuga and Yuta Yamato and Tomokazu Yoneda and Michiko Inoue and Yasuo Sato}, title = {An ECC-based memory architecture with online self-repair capabilities for reliability enhancement}, booktitle = {20th {IEEE} European Test Symposium, {ETS} 2015, Cluj-Napoca, Romania, 25-29 May, 2015}, pages = {1--6}, publisher = {{IEEE}}, year = {2015}, url = {https://doi.org/10.1109/ETS.2015.7138734}, doi = {10.1109/ETS.2015.7138734}, timestamp = {Wed, 16 Oct 2019 14:14:53 +0200}, biburl = {https://dblp.org/rec/conf/ets/MayugaYYIS15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ats/AliYYHI14, author = {Yussuf Ali and Yuta Yamato and Tomokazu Yoneda and Kazumi Hatayama and Michiko Inoue}, title = {Parallel Path Delay Fault Simulation for Multi/Many-Core Processors with {SIMD} Units}, booktitle = {23rd {IEEE} Asian Test Symposium, {ATS} 2014, Hangzhou, China, November 16-19, 2014}, pages = {292--297}, publisher = {{IEEE} Computer Society}, year = {2014}, url = {https://doi.org/10.1109/ATS.2014.61}, doi = {10.1109/ATS.2014.61}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/ats/AliYYHI14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpga/ItoYYHI14, author = {Keita Ito and Tomokazu Yoneda and Yuta Yamato and Kazumi Hatayama and Michiko Inoue}, editor = {Vaughn Betz and George A. Constantinides}, title = {Memory block based scan-BIST architecture for application-dependent {FPGA} testing}, booktitle = {The 2014 {ACM/SIGDA} International Symposium on Field-Programmable Gate Arrays, {FPGA} '14, Monterey, CA, {USA} - February 26 - 28, 2014}, pages = {85--88}, publisher = {{ACM}}, year = {2014}, url = {https://doi.org/10.1145/2554688.2554764}, doi = {10.1145/2554688.2554764}, timestamp = {Tue, 06 Nov 2018 16:58:22 +0100}, biburl = {https://dblp.org/rec/conf/fpga/ItoYYHI14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/ieicet/InoueTYF12, author = {Michiko Inoue and Akira Taketani and Tomokazu Yoneda and Hideo Fujiwara}, title = {Test Pattern Ordering and Selection for High Quality Test Set under Constraints}, journal = {{IEICE} Trans. Inf. Syst.}, volume = {95-D}, number = {12}, pages = {3001--3009}, year = {2012}, url = {https://doi.org/10.1587/transinf.E95.D.3001}, doi = {10.1587/TRANSINF.E95.D.3001}, timestamp = {Sat, 11 Apr 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/ieicet/InoueTYF12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/YiYISKF12, author = {Hyunbean Yi and Tomokazu Yoneda and Michiko Inoue and Yasuo Sato and Seiji Kajihara and Hideo Fujiwara}, title = {A Failure Prediction Strategy for Transistor Aging}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {20}, number = {11}, pages = {1951--1959}, year = {2012}, url = {https://doi.org/10.1109/TVLSI.2011.2165304}, doi = {10.1109/TVLSI.2011.2165304}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/YiYISKF12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/itc/SatoKYHIMUHSS12, author = {Yasuo Sato and Seiji Kajihara and Tomokazu Yoneda and Kazumi Hatayama and Michiko Inoue and Yukiya Miura and Satosni Untake and Takumi Hasegawa and Motoyuki Sato and Kotaro Shimamura}, title = {{DART:} Dependable {VLSI} test architecture and its implementation}, booktitle = {2012 {IEEE} International Test Conference, {ITC} 2012, Anaheim, CA, USA, November 5-8, 2012}, pages = {1--10}, publisher = {{IEEE} Computer Society}, year = {2012}, url = {https://doi.org/10.1109/TEST.2012.6401581}, doi = {10.1109/TEST.2012.6401581}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/itc/SatoKYHIMUHSS12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/itc/YamatoYHI12, author = {Yuta Yamato and Tomokazu Yoneda and Kazumi Hatayama and Michiko Inoue}, title = {A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation}, booktitle = {2012 {IEEE} International Test Conference, {ITC} 2012, Anaheim, CA, USA, November 5-8, 2012}, pages = {1--8}, publisher = {{IEEE} Computer Society}, year = {2012}, url = {https://doi.org/10.1109/TEST.2012.6401549}, doi = {10.1109/TEST.2012.6401549}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/itc/YamatoYHI12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/et/InoueYHF11, author = {Michiko Inoue and Tomokazu Yoneda and Muneo Hasegawa and Hideo Fujiwara}, title = {Balanced Secure Scan: Partial Scan Approach for Secret Information Protection}, journal = {J. Electron. Test.}, volume = {27}, number = {2}, pages = {99--108}, year = {2011}, url = {https://doi.org/10.1007/s10836-011-5204-0}, doi = {10.1007/S10836-011-5204-0}, timestamp = {Fri, 11 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/et/InoueYHF11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/ipsj/KajiharaOY11, author = {Seiji Kajihara and Satoshi Ohtake and Tomokazu Yoneda}, title = {Delay Testing: Improving Test Quality and Avoiding Over-testing}, journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.}, volume = {4}, pages = {117--130}, year = {2011}, url = {https://doi.org/10.2197/ipsjtsldm.4.117}, doi = {10.2197/IPSJTSLDM.4.117}, timestamp = {Tue, 29 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/ipsj/KajiharaOY11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ets/YonedaNISF11, author = {Tomokazu Yoneda and Makoto Nakao and Michiko Inoue and Yasuo Sato and Hideo Fujiwara}, title = {Temperature-Variation-Aware Test Pattern Optimization}, booktitle = {16th European Test Symposium, {ETS} 2011, Trondheim, Norway, May 23-27, 2011}, pages = {214}, publisher = {{IEEE} Computer Society}, year = {2011}, url = {https://doi.org/10.1109/ETS.2011.45}, doi = {10.1109/ETS.2011.45}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/ets/YonedaNISF11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/itc/YonedaHIF11, author = {Tomokazu Yoneda and Keigo Hori and Michiko Inoue and Hideo Fujiwara}, editor = {Bill Eklow and R. D. (Shawn) Blanton}, title = {Faster-than-at-speed test for increased test quality and in-field reliability}, booktitle = {2011 {IEEE} International Test Conference, {ITC} 2011, Anaheim, CA, USA, September 20-22, 2011}, pages = {1--9}, publisher = {{IEEE} Computer Society}, year = {2011}, url = {https://doi.org/10.1109/TEST.2011.6139131}, doi = {10.1109/TEST.2011.6139131}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/itc/YonedaHIF11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/ieicet/YonedaSIIF10, author = {Tomokazu Yoneda and Akiko Shuto and Hideyuki Ichihara and Tomoo Inoue and Hideo Fujiwara}, title = {Design and Optimization of Transparency-Based {TAM} for SoC Test}, journal = {{IEICE} Trans. Inf. Syst.}, volume = {93-D}, number = {6}, pages = {1549--1559}, year = {2010}, url = {https://doi.org/10.1587/transinf.E93.D.1549}, doi = {10.1587/TRANSINF.E93.D.1549}, timestamp = {Sat, 11 Apr 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/ieicet/YonedaSIIF10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/apccas/HussinYYF10, author = {Fawnizu Azmadi Hussin and Thomas Edison Yu and Tomokazu Yoneda and Hideo Fujiwara}, title = {RedSOCs-3D: Thermal-safe test scheduling for 3D-stacked {SOC}}, booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS} 2010, Kuala Lumpur, Malaysia, December 6-9, 2010}, pages = {264--267}, publisher = {{IEEE}}, year = {2010}, url = {https://doi.org/10.1109/APCCAS.2010.5774922}, doi = {10.1109/APCCAS.2010.5774922}, timestamp = {Sun, 25 Jul 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/apccas/HussinYYF10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ats/YonedaITF10, author = {Tomokazu Yoneda and Michiko Inoue and Akira Taketani and Hideo Fujiwara}, title = {Seed Ordering and Selection for High Quality Delay Test}, booktitle = {Proceedings of the 19th {IEEE} Asian Test Symposium, {ATS} 2010, 1-4 December 2010, Shanghai, China}, pages = {313--318}, publisher = {{IEEE} Computer Society}, year = {2010}, url = {https://doi.org/10.1109/ATS.2010.60}, doi = {10.1109/ATS.2010.60}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/ats/YonedaITF10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ets/InoueTYIF10, author = {Michiko Inoue and Akira Taketani and Tomokazu Yoneda and Hiroshi Iwata and Hideo Fujiwara}, title = {Test pattern selection to optimize delay test quality with a limited size of test set}, booktitle = {15th European Test Symposium, {ETS} 2010, Prague, Czech Republic, May 24-28, 2010}, pages = {260}, publisher = {{IEEE} Computer Society}, year = {2010}, url = {https://doi.org/10.1109/ETSYM.2010.5512733}, doi = {10.1109/ETSYM.2010.5512733}, timestamp = {Tue, 28 Apr 2020 11:43:44 +0200}, biburl = {https://dblp.org/rec/conf/ets/InoueTYIF10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iolts/YiYISKF10, author = {Hyunbean Yi and Tomokazu Yoneda and Michiko Inoue and Yasuo Sato and Seiji Kajihara and Hideo Fujiwara}, title = {Aging test strategy and adaptive test scheduling for SoC failure prediction}, booktitle = {16th {IEEE} International On-Line Testing Symposium {(IOLTS} 2010), 5-7 July, 2010, Corfu, Greece}, pages = {21--26}, publisher = {{IEEE} Computer Society}, year = {2010}, url = {https://doi.org/10.1109/IOLTS.2010.5560239}, doi = {10.1109/IOLTS.2010.5560239}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iolts/YiYISKF10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vts/YonedaISF10, author = {Tomokazu Yoneda and Michiko Inoue and Yasuo Sato and Hideo Fujiwara}, title = {Thermal-uniformity-aware X-filling to reduce temperature-induced delay variation for accurate at-speed testing}, booktitle = {28th {IEEE} {VLSI} Test Symposium, {VTS} 2010, April 19-22, 2010, Santa Cruz, California, {USA}}, pages = {188--193}, publisher = {{IEEE} Computer Society}, year = {2010}, url = {https://doi.org/10.1109/VTS.2010.5469578}, doi = {10.1109/VTS.2010.5469578}, timestamp = {Wed, 16 Oct 2019 14:14:54 +0200}, biburl = {https://dblp.org/rec/conf/vts/YonedaISF10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/aspdac/YuYCF09, author = {Thomas Edison Yu and Tomokazu Yoneda and Krishnendu Chakrabarty and Hideo Fujiwara}, editor = {Kazutoshi Wakabayashi}, title = {Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints}, booktitle = {Proceedings of the 14th Asia South Pacific Design Automation Conference, {ASP-DAC} 2009, Yokohama, Japan, January 19-22, 2009}, pages = {793--798}, publisher = {{IEEE}}, year = {2009}, url = {https://doi.org/10.1109/ASPDAC.2009.4796577}, doi = {10.1109/ASPDAC.2009.4796577}, timestamp = {Mon, 03 Jan 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/aspdac/YuYCF09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ets/InoueYHF09, author = {Michiko Inoue and Tomokazu Yoneda and Muneo Hasegawa and Hideo Fujiwara}, title = {Partial Scan Approach for Secret Information Protection}, booktitle = {14th {IEEE} European Test Symposium, {ETS} 2009, Sevilla, Spain, May 25-29, 2009}, pages = {143--148}, publisher = {{IEEE} Computer Society}, year = {2009}, url = {https://doi.org/10.1109/ETS.2009.15}, doi = {10.1109/ETS.2009.15}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/ets/InoueYHF09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/ieicet/HussinYOF08, author = {Fawnizu Azmadi Hussin and Tomokazu Yoneda and Alex Orailoglu and Hideo Fujiwara}, title = {Scheduling Power-Constrained Tests through the SoC Functional Bus}, journal = {{IEICE} Trans. Inf. Syst.}, volume = {91-D}, number = {3}, pages = {736--746}, year = {2008}, url = {https://doi.org/10.1093/ietisy/e91-d.3.736}, doi = {10.1093/IETISY/E91-D.3.736}, timestamp = {Sun, 25 Jul 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/ieicet/HussinYOF08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/ieicet/YonedaMF08, author = {Tomokazu Yoneda and Kimihiko Masuda and Hideo Fujiwara}, title = {Test Scheduling for Multi-Clock Domain SoCs under Power Constraint}, journal = {{IEICE} Trans. Inf. Syst.}, volume = {91-D}, number = {3}, pages = {747--755}, year = {2008}, url = {https://doi.org/10.1093/ietisy/e91-d.3.747}, doi = {10.1093/IETISY/E91-D.3.747}, timestamp = {Sat, 11 Apr 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/ieicet/YonedaMF08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/ieicet/YuYZF08, author = {Thomas Edison Yu and Tomokazu Yoneda and Danella Zhao and Hideo Fujiwara}, title = {Effective Domain Partitioning for Multi-Clock Domain {IP} Core Wrapper Design under Power Constraints}, journal = {{IEICE} Trans. Inf. Syst.}, volume = {91-D}, number = {3}, pages = {807--814}, year = {2008}, url = {https://doi.org/10.1093/ietisy/e91-d.3.807}, doi = {10.1093/IETISY/E91-D.3.807}, timestamp = {Sat, 11 Apr 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/ieicet/YuYZF08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/ieicet/HussinYF08, author = {Fawnizu Azmadi Hussin and Tomokazu Yoneda and Hideo Fujiwara}, title = {On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time}, journal = {{IEICE} Trans. Inf. Syst.}, volume = {91-D}, number = {7}, pages = {1999--2007}, year = {2008}, url = {https://doi.org/10.1093/ietisy/e91-d.7.1999}, doi = {10.1093/IETISY/E91-D.7.1999}, timestamp = {Sun, 25 Jul 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/ieicet/HussinYF08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/ieicet/HussinYF08a, author = {Fawnizu Azmadi Hussin and Tomokazu Yoneda and Hideo Fujiwara}, title = {NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints}, journal = {{IEICE} Trans. Inf. Syst.}, volume = {91-D}, number = {7}, pages = {2008--2017}, year = {2008}, url = {https://doi.org/10.1093/ietisy/e91-d.7.2008}, doi = {10.1093/IETISY/E91-D.7.2008}, timestamp = {Sun, 25 Jul 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/ieicet/HussinYF08a.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/ieicet/YuYCF08, author = {Thomas Edison Yu and Tomokazu Yoneda and Krishnendu Chakrabarty and Hideo Fujiwara}, title = {Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips}, journal = {{IEICE} Trans. Inf. Syst.}, volume = {91-D}, number = {10}, pages = {2440--2448}, year = {2008}, url = {https://doi.org/10.1093/ietisy/e91-d.10.2440}, doi = {10.1093/IETISY/E91-D.10.2440}, timestamp = {Mon, 03 Jan 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/ieicet/YuYCF08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/FujiwaraIYO08, author = {Hideo Fujiwara and Hiroyuki Iwata and Tomokazu Yoneda and Chia Yee Ooi}, title = {A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {27}, number = {9}, pages = {1535--1544}, year = {2008}, url = {https://doi.org/10.1109/TCAD.2008.927757}, doi = {10.1109/TCAD.2008.927757}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/FujiwaraIYO08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ats/YuYOF08, author = {Thomas Edison Yu and Tomokazu Yoneda and Satoshi Ohtake and Hideo Fujiwara}, title = {Identifying Non-Robust Untestable {RTL} Paths in Circuits with Multi-cycle Paths}, booktitle = {17th {IEEE} Asian Test Symposium, {ATS} 2008, Sapporo, Japan, November 24-27, 2008}, pages = {125--130}, publisher = {{IEEE} Computer Society}, year = {2008}, url = {https://doi.org/10.1109/ATS.2008.55}, doi = {10.1109/ATS.2008.55}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/ats/YuYOF08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/YonedaF08, author = {Tomokazu Yoneda and Hideo Fujiwara}, editor = {Donatella Sciuto}, title = {Wrapper and {TAM} Co-Optimization for Reuse of SoC Functional Interconnects}, booktitle = {Design, Automation and Test in Europe, {DATE} 2008, Munich, Germany, March 10-14, 2008}, pages = {1366--1369}, publisher = {{ACM}}, year = {2008}, url = {https://doi.org/10.1109/DATE.2008.4484929}, doi = {10.1109/DATE.2008.4484929}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/date/YonedaF08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/aspdac/HussinYOF07, author = {Fawnizu Azmadi Hussin and Tomokazu Yoneda and Alex Orailoglu and Hideo Fujiwara}, title = {Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses}, booktitle = {Proceedings of the 12th Conference on Asia South Pacific Design Automation, {ASP-DAC} 2007, Yokohama, Japan, January 23-26, 2007}, pages = {720--725}, publisher = {{IEEE} Computer Society}, year = {2007}, url = {https://doi.org/10.1109/ASPDAC.2007.358072}, doi = {10.1109/ASPDAC.2007.358072}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/aspdac/HussinYOF07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ats/YuYCF07, author = {Thomas Edison Yu and Tomokazu Yoneda and Krishnendu Chakrabarty and Hideo Fujiwara}, title = {Thermal-Safe Test Access Mechanism and Wrapper Co-optimization for System-on-Chip}, booktitle = {16th Asian Test Symposium, {ATS} 2007, Beijing, China, October 8-11, 2007}, pages = {187--192}, publisher = {{IEEE}}, year = {2007}, url = {https://doi.org/10.1109/ATS.2007.53}, doi = {10.1109/ATS.2007.53}, timestamp = {Wed, 09 Nov 2022 21:30:34 +0100}, biburl = {https://dblp.org/rec/conf/ats/YuYCF07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ats/YonedaFF07, author = {Tomokazu Yoneda and Yuusuke Fukuda and Hideo Fujiwara}, title = {Test Scheduling for Memory Cores with Built-In Self-Repair}, booktitle = {16th Asian Test Symposium, {ATS} 2007, Beijing, China, October 8-11, 2007}, pages = {199--206}, publisher = {{IEEE}}, year = {2007}, url = {https://doi.org/10.1109/ATS.2007.26}, doi = {10.1109/ATS.2007.26}, timestamp = {Wed, 09 Nov 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/ats/YonedaFF07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ats/HussinYF07, author = {Fawnizu Azmadi Hussin and Tomokazu Yoneda and Hideo Fujiwara}, title = {Area Overhead and Test Time Co-Optimization through NoC Bandwidth Sharing}, booktitle = {16th Asian Test Symposium, {ATS} 2007, Beijing, China, October 8-11, 2007}, pages = {459--462}, publisher = {{IEEE}}, year = {2007}, url = {https://doi.org/10.1109/ATS.2007.22}, doi = {10.1109/ATS.2007.22}, timestamp = {Wed, 09 Nov 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/ats/HussinYF07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/IwataYF07, author = {Hiroyuki Iwata and Tomokazu Yoneda and Hideo Fujiwara}, title = {A {DFT} Method for Time Expansion Model at Register Transfer Level}, booktitle = {Proceedings of the 44th Design Automation Conference, {DAC} 2007, San Diego, CA, USA, June 4-8, 2007}, pages = {682--687}, publisher = {{IEEE}}, year = {2007}, url = {https://doi.org/10.1145/1278480.1278652}, doi = {10.1145/1278480.1278652}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/IwataYF07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/YonedaIF07, author = {Tomokazu Yoneda and Masahiro Imanishi and Hideo Fujiwara}, editor = {Rudy Lauwereins and Jan Madsen}, title = {Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappers}, booktitle = {2007 Design, Automation and Test in Europe Conference and Exposition, {DATE} 2007, Nice, France, April 16-20, 2007}, pages = {231--236}, publisher = {{EDA} Consortium, San Jose, CA, {USA}}, year = {2007}, url = {https://doi.org/10.1109/DATE.2007.364596}, doi = {10.1109/DATE.2007.364596}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/date/YonedaIF07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ets/HussinYF07, author = {Fawnizu Azmadi Hussin and Tomokazu Yoneda and Hideo Fujiwara}, title = {Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints}, booktitle = {12th European Test Symposium, {ETS} 2007, Freiburg, Germany, May 20, 2007}, pages = {35--42}, publisher = {{IEEE} Computer Society}, year = {2007}, url = {https://doi.org/10.1109/ETS.2007.30}, doi = {10.1109/ETS.2007.30}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/ets/HussinYF07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iscas/ZhaoHYF07, author = {Dan Zhao and Ronghua Huang and Tomokazu Yoneda and Hideo Fujiwara}, title = {Power-Aware Multi-Frequency Heterogeneous SoC Test Framework Design with Floor-Ceiling Packing}, booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2007), 27-20 May 2007, New Orleans, Louisiana, {USA}}, pages = {2942--2945}, publisher = {{IEEE}}, year = {2007}, url = {https://doi.org/10.1109/ISCAS.2007.377866}, doi = {10.1109/ISCAS.2007.377866}, timestamp = {Wed, 16 Oct 2019 14:14:49 +0200}, biburl = {https://dblp.org/rec/conf/iscas/ZhaoHYF07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vts/YuYZF07, author = {Thomas Edison Yu and Tomokazu Yoneda and Danella Zhao and Hideo Fujiwara}, title = {Using Domain Partitioning in Wrapper Design for {IP} Cores Under Power Constraints}, booktitle = {25th {IEEE} {VLSI} Test Symposium {(VTS} 2007), 6-10 May 2007, Berkeley, California, {USA}}, pages = {369--374}, publisher = {{IEEE} Computer Society}, year = {2007}, url = {https://doi.org/10.1109/VTS.2007.86}, doi = {10.1109/VTS.2007.86}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/vts/YuYZF07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vts/YonedaSIIF07, author = {Tomokazu Yoneda and Akiko Shuto and Hideyuki Ichihara and Tomoo Inoue and Hideo Fujiwara}, title = {{TAM} Design and Optimization for Transparency-Based SoC Test}, booktitle = {25th {IEEE} {VLSI} Test Symposium {(VTS} 2007), 6-10 May 2007, Berkeley, California, {USA}}, pages = {381--388}, publisher = {{IEEE} Computer Society}, year = {2007}, url = {https://doi.org/10.1109/VTS.2007.78}, doi = {10.1109/VTS.2007.78}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/vts/YonedaSIIF07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/ieicet/MiyazakiYF06, author = {Masahide Miyazaki and Tomokazu Yoneda and Hideo Fujiwara}, title = {A Memory Grouping Method for Reducing Memory {BIST} Logic of System-on-Chips}, journal = {{IEICE} Trans. Inf. Syst.}, volume = {89-D}, number = {4}, pages = {1490--1497}, year = {2006}, url = {https://doi.org/10.1093/ietisy/e89-d.4.1490}, doi = {10.1093/IETISY/E89-D.4.1490}, timestamp = {Sat, 11 Apr 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/ieicet/MiyazakiYF06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/scjapan/YonedaF06, author = {Tomokazu Yoneda and Hideo Fujiwara}, title = {Design for consecutive transparency method of {RTL} circuits}, journal = {Syst. Comput. Jpn.}, volume = {37}, number = {2}, pages = {1--10}, year = {2006}, url = {https://doi.org/10.1002/scj.20417}, doi = {10.1002/SCJ.20417}, timestamp = {Wed, 13 Sep 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/scjapan/YonedaF06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/aspdac/MiyazakiYF06, author = {Masahide Miyazaki and Tomokazu Yoneda and Hideo Fujiwara}, editor = {Fumiyasu Hirose}, title = {A memory grouping method for sharing memory {BIST} logic}, booktitle = {Proceedings of the 2006 Conference on Asia South Pacific Design Automation: {ASP-DAC} 2006, Yokohama, Japan, January 24-27, 2006}, pages = {671--676}, publisher = {{IEEE}}, year = {2006}, url = {https://doi.org/10.1109/ASPDAC.2006.1594763}, doi = {10.1109/ASPDAC.2006.1594763}, timestamp = {Wed, 16 Oct 2019 14:14:52 +0200}, biburl = {https://dblp.org/rec/conf/aspdac/MiyazakiYF06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/YonedaMF06, author = {Tomokazu Yoneda and Kimihiko Masuda and Hideo Fujiwara}, editor = {Georges G. E. Gielen}, title = {Power-constrained test scheduling for multi-clock domain SoCs}, booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe, {DATE} 2006, Munich, Germany, March 6-10, 2006}, pages = {297--302}, publisher = {European Design and Automation Association, Leuven, Belgium}, year = {2006}, url = {https://doi.org/10.1109/DATE.2006.244142}, doi = {10.1109/DATE.2006.244142}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/date/YonedaMF06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccd/HussinYOF06, author = {Fawnizu Azmadi Hussin and Tomokazu Yoneda and Alex Orailoglu and Hideo Fujiwara}, title = {Power-Constrained {SOC} Test Schedules through Utilization of Functional Buses}, booktitle = {24th International Conference on Computer Design {(ICCD} 2006), 1-4 October 2006, San Jose, CA, {USA}}, pages = {230--236}, publisher = {{IEEE}}, year = {2006}, url = {https://doi.org/10.1109/ICCD.2006.4380822}, doi = {10.1109/ICCD.2006.4380822}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccd/HussinYOF06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ats/YonedaTF05, author = {Tomokazu Yoneda and Hisakazu Takakuwa and Hideo Fujiwara}, title = {Power-Constrained Area and Time Co-Optimization for SoCs Based on Consecutive Testability}, booktitle = {14th Asian Test Symposium {(ATS} 2005), 18-21 December 2005, Calcutta, India}, pages = {150--155}, publisher = {{IEEE} Computer Society}, year = {2005}, url = {https://doi.org/10.1109/ATS.2005.88}, doi = {10.1109/ATS.2005.88}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/ats/YonedaTF05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ats/IwataYOF05, author = {Hiroyuki Iwata and Tomokazu Yoneda and Satoshi Ohtake and Hideo Fujiwara}, title = {A {DFT} Method for {RTL} Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency}, booktitle = {14th Asian Test Symposium {(ATS} 2005), 18-21 December 2005, Calcutta, India}, pages = {306--311}, publisher = {{IEEE} Computer Society}, year = {2005}, url = {https://doi.org/10.1109/ATS.2005.8}, doi = {10.1109/ATS.2005.8}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/ats/IwataYOF05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ets/BonhommeYFG04, author = {Yannick Bonhomme and Tomokazu Yoneda and Hideo Fujiwara and Patrick Girard}, title = {An efficient scan tree design for test time reduction}, booktitle = {9th European Test Symposium, {ETS} 2004, Ajaccio, France, May 23-26, 2004}, pages = {174--179}, publisher = {{IEEE} Computer Society}, year = {2004}, url = {https://doi.org/10.1109/ETSYM.2004.1347657}, doi = {10.1109/ETSYM.2004.1347657}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/ets/BonhommeYFG04.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/itc/YonedaUF03, author = {Tomokazu Yoneda and Tetsuo Uchiyama and Hideo Fujiwara}, title = {Area and Time Co-Optimization for System-on-a-Chip based on Consecutive Testability}, booktitle = {Proceedings 2003 International Test Conference {(ITC} 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, {USA}}, pages = {415--422}, publisher = {{IEEE} Computer Society}, year = {2003}, url = {https://doi.org/10.1109/TEST.2003.1270866}, doi = {10.1109/TEST.2003.1270866}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/itc/YonedaUF03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vts/YonedaF03, author = {Tomokazu Yoneda and Hideo Fujiwara}, title = {Design for Consecutive Transparency of Cores in System-on-a-Chip}, booktitle = {21st {IEEE} {VLSI} Test Symposium {(VTS} 2003), 27 April - 1 May 2003, Napa Valley, CA, {USA}}, pages = {287--292}, publisher = {{IEEE} Computer Society}, year = {2003}, url = {https://doi.org/10.1109/VTEST.2003.1197665}, doi = {10.1109/VTEST.2003.1197665}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/vts/YonedaF03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/et/YonedaF02, author = {Tomokazu Yoneda and Hideo Fujiwara}, title = {Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores}, journal = {J. Electron. Test.}, volume = {18}, number = {4-5}, pages = {487--501}, year = {2002}, url = {https://doi.org/10.1023/A:1016553809732}, doi = {10.1023/A:1016553809732}, timestamp = {Fri, 11 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/et/YonedaF02.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ats/YonedaF01, author = {Tomokazu Yoneda and Hideo Fujiwara}, title = {A {DFT} Method for Core-Based Systems-on-a-Chip Based on Consecutive Testability}, booktitle = {10th Asian Test Symposium {(ATS} 2001), 19-21 November 2001, Kyoto, Japan}, pages = {193--198}, publisher = {{IEEE} Computer Society}, year = {2001}, url = {https://doi.org/10.1109/ATS.2001.990280}, doi = {10.1109/ATS.2001.990280}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/ats/YonedaF01.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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