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Cecil Accetti

Cecil Accetti R. de A. Melo

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affiliation: Shanghai Jiaotong University, School of Electronic Information and Electrical Engineering, China

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2020 – today

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2022
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Cecil Accetti, Rendong Ying, Peilin Liu:
Structured Combinators for Efficient Graph Reduction. IEEE Comput. Archit. Lett. 21(2): 73-76 (2022)
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Cecil Accetti, Peilin Liu:
Architectural Support for Functional Programming. VLSI-SoC 2022: 1-2
2020
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Cecil Accetti R. de A. Melo, Peilin Liu, Rendong Ying:
A Platform for Full-Stack Functional Programming. ISCAS 2020: 1-5

2010 – 2019

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2018
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Rongdi Sun, Peilin Liu, Cecil Accetti, Abid A. Naqvi, Haroon Ahmed, Jiuchao Qian:
A 974GOPS/W Multi-level Parallel Architecture for Binary Weight Network Acceleration. ISCAS 2018: 1-4
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Pedro J. A. Ishimaru, Antonyus P. A. Ferreira, Vanessa O. Ogg, Cecil Accetti R. de A. Melo, Edna Natividade da Silva Barros:
An FPGA-Based RFID Baseband Processor Using a RISC-V Platform. SBCCI 2018: 1-6
2017
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Rongdi Sun, Peilin Liu, Jun Wang, Cecil Accetti, Abid A. Naqvi:
A 42fps full-HD ORB feature extraction accelerator with reduced memory overhead. FPT 2017: 183-190
2016
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Cecil Accetti R. de A. Melo, Edna Barros:
Oolong: A Baseband processor extension to the RISC-V ISA. ASAP 2016: 241-242
2012
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Cecil Accetti R. de A. Melo, Ricardo E. de Souza:
FPGA-based digital direct-conversion transceiver for Nuclear Magnetic Resonance Systems. SBCCI 2012: 1-5

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