ask others

Kai-Yuan Chao

> Home > Persons

Refine list

refinements active!

zoomed in on ?? of ?? records

view refined list in

export refined list as

showing all ?? records

2010 – today

see FAQ

What is the meaning of the colors in the publication lists?

2017
[c29]
- view
  - electronic edition via DOI
- export record
  dblp key:
  - conf/aspdac/HanLEKCW17
- ask others
- share record
  short URL:
  - https://dblp.org/rec/conf/aspdac/HanLEKCW17
Szu-Yuan Han, Wen-Hao Liu, Rickard Ewetz, Cheng-Kok Koh, Kai-Yuan Chao, Ting-Chi Wang:
Delay-driven layer assignment for advanced technology nodes. ASP-DAC 2017: 456-462
2014
[c28]
- view
  - electronic edition via DOI
- export record
  dblp key:
  - conf/glvlsi/EwetzLCWK14
- ask others
- share record
  short URL:
  - https://dblp.org/rec/conf/glvlsi/EwetzLCWK14
Rickard Ewetz, Wen-Hao Liu, Kai-Yuan Chao, Ting-Chi Wang, Cheng-Kok Koh:
A study on the use of parallel wiring techniques for sub-20nm designs. ACM Great Lakes Symposium on VLSI 2014: 129-134
2013
[j9]
- view
  - electronic edition via DOI
- export record
  dblp key:
  - journals/tcad/LiuKLC13
- ask others
- share record
  short URL:
  - https://dblp.org/rec/journals/tcad/LiuKLC13
Wen-Hao Liu, Wei-Chun Kao, Yih-Lang Li, Kai-Yuan Chao:
NCTU-GR 2.0: Multithreaded Collision-Aware Global Routing With Bounded-Length Maze Routing. IEEE Trans. on CAD of Integrated Circuits and Systems 32(5): 709-722 (2013)
[c27]
- view
  - electronic edition via DOI
- export record
  dblp key:
  - conf/aspdac/ShihHLCC13
- ask others
- share record
  short URL:
  - https://dblp.org/rec/conf/aspdac/ShihHLCC13
Xin-Wei Shih, Tzu-Hsuan Hsu, Hsu-Chieh Lee, Yao-Wen Chang, Kai-Yuan Chao:
Symmetrical buffered clock-tree synthesis with supply-voltage alignment. ASP-DAC 2013: 447-452
2012
[j8]
- view
  - electronic edition via DOI
- export record
  dblp key:
  - journals/esticas/ZhangWCD12
- ask others
- share record
  short URL:
  - https://dblp.org/rec/journals/esticas/ZhangWCD12
Hongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao, Liang Deng:
A Practical Low-Power Nonregular Interconnect Design With Manufacturing for Design Approach. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(2): 322-332 (2012)
[c26]
- view
  - electronic edition via DOI
- export record
  dblp key:
  - conf/aspdac/DuZWC12
- ask others
- share record
  short URL:
  - https://dblp.org/rec/conf/aspdac/DuZWC12
Yuelin Du, Hongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao:
Hybrid lithography optimization with E-Beam and immersion processes for 16nm 1D gridded design. ASP-DAC 2012: 707-712
[c25]
- view
  - electronic edition via DOI
  - electronic edition @ ieee.org
- export record
  dblp key:
  - conf/iccad/LuKSCCH12
- ask others
- share record
  short URL:
  - https://dblp.org/rec/conf/iccad/LuKSCCH12
Shih-Lien Lu, Tanay Karnik, Ganapati Srinivasa, Kai-Yuan Chao, Doug Carmean, Jim Held:
Scaling the "Memory Wall": Designer track. ICCAD 2012: 271-272
2011
[c24]
- view
  - electronic edition via DOI
  - electronic edition @ acm.org
- export record
  dblp key:
  - conf/aspdac/LinLWKC11
- ask others
- share record
  short URL:
  - https://dblp.org/rec/conf/aspdac/LinLWKC11
Shing-Tung Lin, Kuang-Yao Lee, Ting-Chi Wang, Cheng-Kok Koh, Kai-Yuan Chao:
Simultaneous redundant via insertion and line end extension for yield optimization. ASP-DAC 2011: 633-638
[c23]
- view
  - electronic edition via DOI
  - electronic edition @ acm.org
- export record
  dblp key:
  - conf/aspdac/ZhangDWC11
- ask others
- share record
  short URL:
  - https://dblp.org/rec/conf/aspdac/ZhangDWC11
Hongbo Zhang, Yuelin Du, Martin D. F. Wong, Kai-Yuan Chao:
Mask cost reduction with circuit performance consideration for self-aligned double patterning. ASP-DAC 2011: 787-792
[c22]
- view
- export record
  dblp key:
  - conf/iccad/LiuLC11
- ask others
- share record
  short URL:
  - https://dblp.org/rec/conf/iccad/LiuLC11
Wen-Hao Liu, Yih-Lang Li, Kai-Yuan Chao:
High-quality global routing for multiple dynamic supply voltage designs. ICCAD 2011: 263-269
[c21]
- view
  - electronic edition via DOI
- export record
  dblp key:
  - conf/isqed/ZhangDWC11
- ask others
- share record
  short URL:
  - https://dblp.org/rec/conf/isqed/ZhangDWC11
Hongbo Zhang, Yuelin Du, Martin D. F. Wong, Kai-Yuan Chao:
Lithography-aware layout modification considering performance impact. ISQED 2011: 437-441
2010
[j7]
- view
  - electronic edition via DOI
- export record
  dblp key:
  - journals/tcad/LeeWKC10
- ask others
- share record
  short URL:
  - https://dblp.org/rec/journals/tcad/LeeWKC10
Kuang-Yao Lee, Ting-Chi Wang, Cheng-Kok Koh, Kai-Yuan Chao:
Optimal Double Via Insertion With On-Track Preference. IEEE Trans. on CAD of Integrated Circuits and Systems 29(2): 318-323 (2010)
[c20]
- view
  - electronic edition via DOI
  - electronic edition @ acm.org
- export record
  dblp key:
  - conf/aspdac/MaWC10
- ask others
- share record
  short URL:
  - https://dblp.org/rec/conf/aspdac/MaWC10
Qiang Ma, Martin D. F. Wong, Kai-Yuan Chao:
Configurable multi-product floorplanning. ASP-DAC 2010: 549-554
[c19]
- view
  - electronic edition via DOI
  - electronic edition @ acm.org
- export record
  dblp key:
  - conf/aspdac/ZhangWC10
- ask others
- share record
  short URL:
  - https://dblp.org/rec/conf/aspdac/ZhangWC10
Hongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao:
On process-aware 1-D standard cell design. ASP-DAC 2010: 838-842
[c18]
- view
  - electronic edition via DOI
- export record
  dblp key:
  - conf/dac/LiuKLC10
- ask others
- share record
  short URL:
  - https://dblp.org/rec/conf/dac/LiuKLC10
Wen-Hao Liu, Wei-Chun Kao, Yih-Lang Li, Kai-Yuan Chao:
Multi-threaded collision-aware global routing with bounded-length maze routing. DAC 2010: 200-205

2000 – 2009

see FAQ

What is the meaning of the colors in the publication lists?

2009
[c17]
- view
  - electronic edition via DOI
- export record
  dblp key:
  - conf/dac/JiangHCC09
- ask others
- share record
  short URL:
  - https://dblp.org/rec/conf/dac/JiangHCC09
Zhe-Wei Jiang, Meng-Kai Hsu, Yao-Wen Chang, Kai-Yuan Chao:
Spare-cell-aware multilevel analytical placement. DAC 2009: 430-435
[c16]
- view
  - electronic edition via DOI
- export record
  dblp key:
  - conf/ispd/ZhangWCD09
- ask others
- share record
  short URL:
  - https://dblp.org/rec/conf/ispd/ZhangWCD09
Hongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao, Liang Deng:
Wire shaping is practical. ISPD 2009: 131-138
2008
[j6]
- view
  - electronic edition via DOI
- export record
  dblp key:
  - journals/tcad/XiangCPW08
- ask others
- share record
  short URL:
  - https://dblp.org/rec/journals/tcad/XiangCPW08
Hua Xiang, Kai-Yuan Chao, Ruchir Puri, Martin D. F. Wong:
Is Your Layout-Density Verification Exact? - A Fast Exact Deep Submicrometer Density Calculation Algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 621-632 (2008)
[j5]
- view
  - electronic edition via DOI
- export record
  dblp key:
  - journals/tcad/XiangDPCW08
- ask others
- share record
  short URL:
  - https://dblp.org/rec/journals/tcad/XiangDPCW08
Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong:
Fast Dummy-Fill Density Analysis With Coupling Constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 633-642 (2008)
[j4]
- view
  - electronic edition via DOI
- export record
  dblp key:
  - journals/tcad/LeeKWC08
- ask others
- share record
  short URL:
  - https://dblp.org/rec/journals/tcad/LeeKWC08
Kuang-Yao Lee, Cheng-Kok Koh, Ting-Chi Wang, Kai-Yuan Chao:
Fast and Optimal Redundant Via Insertion. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2197-2208 (2008)
[c15]
- view
  - electronic edition via DOI
- export record
  dblp key:
  - conf/ispd/LeeKWC08
- ask others
- share record
  short URL:
  - https://dblp.org/rec/conf/ispd/LeeKWC08
Kuang-Yao Lee, Cheng-Kok Koh, Ting-Chi Wang, Kai-Yuan Chao:
Optimal post-routing redundant via insertion. ISPD 2008: 111-117
2007
[c14]
- view
- export record
  dblp key:
  - conf/aspdac/DengWCX07
- ask others
- share record
  short URL:
  - https://dblp.org/rec/conf/aspdac/DengWCX07
Liang Deng, Martin D. F. Wong, Kai-Yuan Chao, Hua Xiang:
Coupling-aware Dummy Metal Insertion for Lithography. ASP-DAC 2007: 13-18
[c13]
- view
  - electronic edition via DOI
- export record
  dblp key:
  - conf/ispd/XiangDPCW07
- ask others
- share record
  short URL:
  - https://dblp.org/rec/conf/ispd/XiangDPCW07
Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong:
Dummy fill density analysis with coupling constraints. ISPD 2007: 3-10
[c12]
- view
  - electronic edition via DOI
- export record
  dblp key:
  - conf/ispd/XiangCPW07
- ask others
- share record
  short URL:
  - https://dblp.org/rec/conf/ispd/XiangCPW07
Hua Xiang, Kai-Yuan Chao, Ruchir Puri, Martin D. F. Wong:
Is your layout density verification exact?: a fast exact algorithm for density calculation. ISPD 2007: 19-26
2006
[j3]
- view
  - electronic edition via DOI
- export record
  dblp key:
  - journals/tcad/XiangCW06
- ask others
- share record
  short URL:
  - https://dblp.org/rec/journals/tcad/XiangCW06
Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong:
An ECO routing algorithm for eliminating coupling-capacitance violations. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1754-1762 (2006)
[c11]
- view
- export record
  dblp key:
  - conf/iccad/LeeWC06
- ask others
- share record
  short URL:
  - https://dblp.org/rec/conf/iccad/LeeWC06
Kuang-Yao Lee, Ting-Chi Wang, Kai-Yuan Chao:
Post-routing redundant via insertion and line end extension with via density consideration. ICCAD 2006: 633-640
2005
[c10]
- view
  - electronic edition via DOI
  - electronic edition @ ieeecomputersociety.org
- export record
  dblp key:
  - conf/isqed/XiangCW05
- ask others
- share record
  short URL:
  - https://dblp.org/rec/conf/isqed/XiangCW05
Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong:
Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer. ISQED 2005: 181-186
2004
[j2]
- view
  - electronic edition via DOI
- export record
  dblp key:
  - journals/tcad/JiangCJC04
- ask others
- share record
  short URL:
  - https://dblp.org/rec/journals/tcad/JiangCJC04
Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao:
Simultaneous floor plan and buffer-block optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 694-703 (2004)
[c9]
- view
  - electronic edition via DOI
- export record
  dblp key:
  - conf/ispd/XiangCW04
- ask others
- share record
  short URL:
  - https://dblp.org/rec/conf/ispd/XiangCW04
Hua Xiang, Kai-Yuan Chao, D. F. Wong:
An ECO algorithm for eliminating crosstalk violations. ISPD 2004: 41-46
2003
[c8]
- view
  - electronic edition via DOI
- export record
  dblp key:
  - conf/aspdac/JiangCJC03
- ask others
- share record
  short URL:
  - https://dblp.org/rec/conf/aspdac/JiangCJC03
Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao:
Simultaneous floorplanning and buffer block planning. ASP-DAC 2003: 431-434
2002
[c7]
- view
- export record
  dblp key:
  - conf/date/LuZKC02
- ask others
- share record
  short URL:
  - https://dblp.org/rec/conf/date/LuZKC02
Ruibing Lu, Guoan Zhong, Cheng-Kok Koh, Kai-Yuan Chao:
Flip-Flop and Repeater Insertion for Early Interconnect Planning. DATE 2002: 690-695
[c6]
- view
- export record
  dblp key:
  - conf/iccad/XiangCW02
- ask others
- share record
  short URL:
  - https://dblp.org/rec/conf/iccad/XiangCW02
Hua Xiang, Kai-Yuan Chao, D. F. Wong:
ECO algorithms for removing overlaps between power rails and signal wires. ICCAD 2002: 67-74

1990 – 1999

see FAQ

What is the meaning of the colors in the publication lists?

1998
[j1]
- view
  - electronic edition via DOI
- export record
  dblp key:
  - journals/vlsi/ThakurCW98
- ask others
- share record
  short URL:
  - https://dblp.org/rec/journals/vlsi/ThakurCW98
Shashidhar Thakur, Kai-Yuan Chao, D. F. Wong:
Minimum Crosstalk Vertical Layer Assignment for Three-Layer VHV Channel Routing. VLSI Design 1998(1): 73-84 (1998)
1995
[c5]
- view
- export record
  dblp key:
  - conf/iccad/ChaoW95
- ask others
- share record
  short URL:
  - https://dblp.org/rec/conf/iccad/ChaoW95
Kai-Yuan Chao, D. F. Wong:
Signal integrity optimization on the pad assignment for high-speed VLSI design. ICCAD 1995: 720-725
[c4]
- view
  - electronic edition via DOI
  - electronic edition @ ieeecomputersociety.org
- export record
  dblp key:
  - conf/iccd/ChaoW95
- ask others
- share record
  short URL:
  - https://dblp.org/rec/conf/iccd/ChaoW95
Kai-Yuan Chao, D. F. Wong:
Thermal placement for high-performance multichip modules. ICCD 1995: 218-223
[c3]
- view
  - electronic edition via DOI
- export record
  dblp key:
  - conf/iscas/ChaoW95
- ask others
- share record
  short URL:
  - https://dblp.org/rec/conf/iscas/ChaoW95
Kai-Yuan Chao, D. F. Wong:
Floorplanning for Low Power Designs. ISCAS 1995: 45-48
[c2]
- view
  - electronic edition via DOI
- export record
  dblp key:
  - conf/iscas/ThakurCW95
- ask others
- share record
  short URL:
  - https://dblp.org/rec/conf/iscas/ThakurCW95
Shashidhar Thakur, Kai-Yuan Chao, D. F. Wong:
An Optimal Layer Assignment Algorithm for Minimizing Crosstalk for Three Layer VHV Channel Routing. ISCAS 1995: 207-210
1994
[c1]
- view
- export record
  dblp key:
  - conf/iccad/ChaoW94
- ask others
- share record
  short URL:
  - https://dblp.org/rec/conf/iccad/ChaoW94
Kai-Yuan Chao, D. F. Wong:
Layer assignment for high-performance multi-chip modules. ICCAD 1994: 680-685

Coauthor Index

see FAQ

maintained by

, founded at