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ORCIDWenjay Hsu
Person information
- affiliation: Oracle Microelectronics, Santa Clara, CA, USA
- affiliation (PhD 1991): University of Southern California, Los Angeles, CA, USA
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2010 – 2019
- 2016
[j5]Georgios K. Konstadinidis, Hongping Penny Li, Francis Schumacher, Venkatram Krishnaswamy, Hoyeol Cho, Sudesna Dash, Robert P. Masleid, Chaoyang Zheng, Yuanjung David Lin, Paul Loewenstein, Heechoul Park, Vijay Srinivasan, Dawei Huang, Changku Hwang, Wenjay Hsu, Curtis McAllister, Jeffrey Brooks, Ha Pham, Sebastian Turullols, Yifan YangGong, Robert T. Golla, Alan P. Smith, Ali Vahidsafa:
SPARC M7: A 20 nm 32-Core 64 MB L3 Cache Processor. IEEE J. Solid State Circuits 51(1): 79-91 (2016)- 2015
- [c3]Penny Li, Jinuk Luke Shin, Georgios K. Konstadinidis, Francis Schumacher, Venkatram Krishnaswamy, Hoyeol Cho, Sudesna Dash, Robert P. Masleid, Chaoyang Zheng, Yuanjung David Lin, Paul Loewenstein, Heechoul Park, Vijay Srinivasan, Dawei Huang, Changku Hwang, Wenjay Hsu, Curtis McAllister:
4.2 A 20nm 32-Core 64MB L3 cache SPARC M7 processor. ISSCC 2015: 1-3
2000 – 2009
- 2005
- [j4]Hugh McIntyre, Dennis Wendell, K. James Lin, P. Kaushik, Suresh Seshadri, Alfred Wang, V. Sundararaman, Ping Wang, Song Kim, Wen-Jay Hsu, Hee-Choul Park, Gideon Levinsky, Jiejun Lu, M. Chirania, Raymond A. Heald, Paul Lazar, Sanjaya Dharmasena:
A 4-MB on-chip L2 cache for a 90-nm 1.6-GHz 64-bit microprocessor. IEEE J. Solid State Circuits 40(1): 52-59 (2005) - 2000
- [j3]Raymond A. Heald, Kathirgamar Aingaran, Chaim Amir, Michael Ang, Michael Boland, Pankaj Dixit, Gary Gouldsberry, Dale Greenley, Joel Grinberg, Jason M. Hart, Tim Horel, Wen-Jay Hsu, James M. Kaku, Chin Kim, Song Kim, Fabian Klass, Hang Kwan, Gary Lauterbach, Roger Lo, Hugh McIntyre, Anup Mehta, David Murata, Sophie Nguyen, Yet-Ping Pai, Subeer Patel, Ken Shin, Kenway Tam, Sai Vishwanthaiah, John Wu, Gin Yee, Eileen You:
A third-generation SPARC V9 64-b microprocessor. IEEE J. Solid State Circuits 35(11): 1526-1538 (2000)
1990 – 1999
- 1994
- [j2]Sudhir M. Gowda, Bing J. Sheu, Wen-Jay Hsu:
Testing of programmable analog neural network chips. J. VLSI Signal Process. 8(3): 267-282 (1994) - 1991
- [c2]Wen-Jay Hsu, Bing J. Sheu, Sudhir M. Gowda:
Testing of Analog Neural Array-Processor Chips. ICCD 1991: 118-121
1980 – 1989
- 1989
- [c1]Wen-Jay Hsu, Bing J. Sheu, Vance C. Tyree:
Digital and analog integrated-circuit design with built-in reliability. ICCD 1989: 496-499 - 1988
- [j1]Bing J. Sheu, Wen-Jay Hsu, P. K. Ko:
An MOS transistor charge model for VLSI design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(4): 520-527 (1988)
Coauthor Index
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last updated on 2023-09-27 22:47 CEST by the dblp team
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