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ORCIDRam Krishnamurthy 0001
Ram K. Krishnamurthy – Ram Kumar Krishnamurthy
Person information
- affiliation: Intel Corporation, Circuit Research Lab, Hillsboro, OR, USA
- affiliation (PhD 1997): Carnegie Mellon University, Pittsburgh, PA, USA
- affiliation: State University of New York at Buffalo, Center of Excellence for Document Analysis and Recognition, NY, USA
Other persons with the same name
- Ram Krishnamurthy 0002 — University of Alberta, Department of Biological Sciences, Edmonton, AB, Canada (and 1 more)
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2020 – today
- 2024
[j41]Chuan-Tung Lin
, Dewei Wang, Bo Zhang, Gregory K. Chen, Phil C. Knag, Ram Kumar Krishnamurthy, Mingoo Seok:
DIMCA: An Area-Efficient Digital In-Memory Computing Macro Featuring Approximate Arithmetic Hardware in 28 nm. IEEE J. Solid State Circuits 59(3): 960-971 (2024)- 2023
- [j40]Gregory K. Chen, Phil C. Knag, Carlos Tokunaga, Ram K. Krishnamurthy:
An Eight-Core RISC-V Processor With Compute Near Last Level Cache in Intel 4 CMOS. IEEE J. Solid State Circuits 58(4): 1117-1128 (2023) - [c97]Dewei Wang, Jonghyun Oh, Gregory K. Chen, Phil C. Knag, Ram K. Krishnamurthy, Mingoo Seok:
microASR: 32-μW Real-Time Automatic Speech Recognition Chip featuring a Bio-Inspired Neuron Model and Digital SRAM-based Compute-In-Memory Hardware. ESSCIRC 2023: 421-424 - [c96]Zhaoqing Wang, Mao Li, Suhwan Kim, Nachiket V. Desai, Ram K. Krishnamurthy, Orlando Lazaro, Andres Blanco, Xin Zhang, Mingoo Seok:
93.89% Peak Efficiency 24V-to-1V DC-DC Converter with Fast In-Situ Efficiency Tracking and Power-FET Code Roaming. ESSCIRC 2023: 437-440 - 2022
- [j39]Zhiyuan Zhou, Nghia Tang, Bai Nguyen, Wookpyo Hong, Partha Pratim Pande, Ram K. Krishnamurthy, Deukhyoun Heo:
An Inductor-First Single-Inductor Multiple-Output Hybrid DC-DC Converter With Integrated Flying Capacitor for SoC Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 69(12): 4823-4836 (2022) - [c95]Amit Agarwal, Steven Hsu, Mark A. Anders, Gunjan Pandya, Ram Krishnamurthy, James W. Tschanz, Vivek De:
On-Chip High-Resolution Timing Characterization Circuits for Memory IPs. ESSCIRC 2022: 377-380 - [c94]Dewei Wang, Chuan-Tung Lin, Gregory K. Chen, Phil C. Knag, Ram Kumar Krishnamurthy, Mingoo Seok:
DIMC: 2219TOPS/W 2569F2/b Digital In-Memory Computing Macro in 28nm Based on Approximate Arithmetic Hardware. ISSCC 2022: 266-268 - [c93]Steven Hsu, Amit Agarwal, Mark A. Anders, Arnab Raha, Raymond Sung, Deepak Mathaikutty, Ram Krishnamurthy, James W. Tschanz, Vivek De:
2.4GHz, Double-Buffered, 4kb Standard-Cell-Based Register File with Low-Power Mixed-Frequency Clocking for Machine Learning Accelerators. VLSI Technology and Circuits 2022: 22-23 - [c92]Gregory K. Chen, Phil C. Knag, Carlos Tokunaga, Ram K. Krishnamurthy:
An 8-core RISC-V Processor with Compute near Last Level Cache in Intel 4 CMOS. VLSI Technology and Circuits 2022: 68-69 - 2021
- [j38]Phil C. Knag, Gregory K. Chen, Huseyin Ekin Sumbul, Raghavan Kumar, Steven K. Hsu, Amit Agarwal, Monodeep Kar, Seongjong Kim, Mark A. Anders, Himanshu Kaul, Ram K. Krishnamurthy:
A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOS. IEEE J. Solid State Circuits 56(4): 1082-1092 (2021) - [j37]Sriram R. Vangal, Somnath Paul, Steven Hsu, Amit Agarwal, Saurabh Kumar, Ram Krishnamurthy, Harish Krishnamurthy, James W. Tschanz, Vivek De, Chris H. Kim:
Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities. IEEE Trans. Very Large Scale Integr. Syst. 29(5): 843-856 (2021) - 2020
- [j36]Raghavan Kumar, Vikram B. Suresh, Monodeep Kar, Sudhir Satpathy, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram K. Krishnamurthy, Vivek De, Sanu K. Mathew:
A 4900- $\mu$ m2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition. IEEE J. Solid State Circuits 55(4): 945-955 (2020) - [c91]Amit Agarwal, Steven Hsu, Simeon Realov, Mark A. Anders, Gregory K. Chen, Monodeep Kar, Raghavan Kumar, Huseyin Sumbul, Phil C. Knag, Himanshu Kaul, Sanu Mathew, Mahesh Kumashikar, Ram Krishnamurthy, Vivek De:
25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS. ISSCC 2020: 392-394 - [c90]Mark A. Anders, Himanshu Kaul, Seongjong Kim, Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Phil C. Knag, Monodeep Kar, Steven K. Hsu, Amit Agarwal, Vikram B. Suresh, Sanu K. Mathew, Ram K. Krishnamurthy, Vivek De:
25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range. ISSCC 2020: 396-398 - [c89]Steven Hsu, Amit Agarwal, Simeon Realov, Mark A. Anders, Gregory K. Chen, Monodeep Kar, Raghavan Kumar, Huseyin Sumbul, Phil C. Knag, Himanshu Kaul, Vikram B. Suresh, Sanu Mathew, Iqbal Rajwani, Satish Damaraju, Ram Krishnamurthy, Vivek De:
Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS. VLSI Circuits 2020: 1-2 - [c88]Monodeep Kar, Amit Agarwal, Steven Hsu, David Moloney, Gregory K. Chen, Raghavan Kumar, Huseyin Sumbul, Phil C. Knag, Mark A. Anders, Himanshu Kaul, Jonathan Byrne, Luca Sarti, Ram Krishnamurthy, Vivek De:
A Ray-Casting Accelerator in 10nm CMOS for Efficient 3D Scene Reconstruction in Edge Robotics and Augmented Reality Applications. VLSI Circuits 2020: 1-2 - [c87]Phil C. Knag, Gregory K. Chen, Huseyin Ekin Sumbul, Raghavan Kumar, Mark A. Anders, Himanshu Kaul, Steven K. Hsu, Amit Agarwal, Monodeep Kar, Seongjong Kim, Ram K. Krishnamurthy:
A 617 TOPS/W All Digital Binary Neural Network Accelerator in 10nm FinFET CMOS. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j35]Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Phil C. Knag, Ram K. Krishnamurthy:
A 4096-Neuron 1M-Synapse 3.8-pJ/SOP Spiking Neural Network With On-Chip STDP Learning and Sparse Weights in 10-nm FinFET CMOS. IEEE J. Solid State Circuits 54(4): 992-1002 (2019) - [j34]Sudhir Satpathy, Sanu K. Mathew, Raghavan Kumar, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram K. Krishnamurthy, Vivek De:
An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS. IEEE J. Solid State Circuits 54(4): 1074-1085 (2019) - [c86]Himanshu Kaul, Mark A. Anders, Sanu Mathew, Seongjong Kim, Ram Krishnamurthy:
Optimized Fused Floating-Point Many-Term Dot-Product Hardware for Machine Learning Accelerators. ARITH 2019: 84-87 - [c85]Amit Agarwal, Steven Hsu, Monodeep Kar, Mark A. Anders, Himanshu Kaul, Raghavan Kumar, Vikram B. Suresh, Sanu Mathew, Ram Krishnamurthy, Vivek De:
A 54% Power-Saving Static Fully-Interruptible Single-Phase-Clocked Shared-Keeper Flip-Flop in 14nm CMOS. A-SSCC 2019: 137-140 - [c84]Sudhir Satpathy, Vikram B. Suresh, Raghavan Kumar, Vinodh Gopal, James Guilford, Kirk Yap, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Sanu Mathew:
A 220-900mV 179Mcode/s 36pJ/code Canonical Huffman Encoder for DEFLATE Compression in 14nm CMOS. CICC 2019: 1-4 - [c83]Vikram B. Suresh, Sudhir Satpathy, Raghavan Kumar, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Sanu Mathew:
A 225-950mV 1.5Tbps/W Whirlpool Hashing Accelerator for Secure Automotive Platforms in 14nm CMOS. CICC 2019: 1-4 - [c82]Eriko Nurvitadhi, Dongup Kwon, Ali Jafari, Andrew Boutros, Jaewoong Sim, Phillip Tomson, Huseyin Sumbul, Gregory K. Chen, Phil C. Knag, Raghavan Kumar, Ram Krishnamurthy, Sergey Gribok, Bogdan Pasca, Martin Langhammer, Debbie Marr, Aravind Dasu:
Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs. FCCM 2019: 199-207 - [c81]Eriko Nurvitadhi, Dongup Kwon, Ali Jafari, Andrew Boutros, Jaewoong Sim, Phillip Tomson, Huseyin Sumbul, Gregory K. Chen, Phil C. Knag, Raghavan Kumar, Ram Krishnamurthy, Debbie Marr, Sergey Gribok, Bogdan Pasca, Martin Langhammer, Aravind Dasu:
Evaluating and Enhancing Intel® Stratix® 10 FPGAs for Persistent Real-Time AI. FPGA 2019: 119 - [c80]Ram K. Krishnamurthy:
Wednesday Plenary: Machine Learning and Hardware Security Technologies for the Nanoscale era: Challenges & Opportunities. SoCC 2019: 1-3 - [c79]Vikram B. Suresh, Sudhir Satpathy, Raghavan Kumar, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Vivek De, Sanu Mathew:
A 250Mv, 0.063J/Ghash Bitcoin Mining Engine in 14nm CMOS Featuring Dual-Vcc Sha256 Datapath and 3-Phase Latch Based Clocking. VLSI Circuits 2019: 32- - [c78]Steven Hsu, Amit Agarwal, Monodeep Kar, Mark A. Anders, Himanshu Kaul, Raghavan Kumar, Sudhir Satpathy, Vikram B. Suresh, Sanu Mathew, Ram Krishnamurthy, Vivek De:
A Microwatt-Class Always-On Sensor Fusion Engine Featuring Ultra-Low-Power AOI Clocked Circuits in 14nm CMOS. VLSI Circuits 2019: 50- - [c77]Raghavan Kumar, Vikram B. Suresh, Monodeep Kar, Sudhir Satpathy, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram Krishnamurthy, Vivek De, Sanu Mathew:
A 4900×m2 839Mbps Side-Channel Attack Resistant AES-128 in 14nm CMOS with Heterogeneous Sboxes, Linear Masked MixColumns and Dual-Rail Key Addition. VLSI Circuits 2019: 234- - [c76]Sudhir Satpathy, Vikram B. Suresh, Raghavan Kumar, Vinodh Gopal, James Guilford, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Vivek De, Sanu Mathew:
A 1.4GHz 20.5Gbps GZIP decompression accelerator in 14nm CMOS featuring dual-path out-of-order speculative Huffman decoder and multi-write enabled register file array. VLSI Circuits 2019: 238- - 2018
- [c75]Himanshu Kaul, Mark A. Anders, Sanu Mathew, Vikram B. Suresh, Sudhir Satpathy, Amit Agarwal, Steven Hsu, Ram Krishnamurthy:
Ultra-Lightweight 548-1080 Gate 166Gbps/W-12.6Tbps/W SIMON 32/64 Cipher Accelerators for IoT in 14nm Tri-gate CMOS. A-SSCC 2018: 1-4 - [c74]Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Vinodh Gopal, James Guilford, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy:
A 280mV 3.1pJ/code Huffman Decoder for DEFLATE Decompression Featuring Opportunistic Code Skip and 3-way Symbol Generation in 14nm Tri-gate CMOS. A-SSCC 2018: 263-266 - [c73]Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Ram Krishnamurthy:
Ultra-low energy circuit building blocks for security technologies. DATE 2018: 391-394 - [c72]Vikram B. Suresh, Sudhir Satpathy, Sanu Mathew, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy:
A 230mV-950mV 2.8Tbps/W Unified SHA256/SM3 Secure Hashing Hardware Accelerator in 14nm Tri-Gate CMOS. ESSCIRC 2018: 98-101 - [c71]Mark A. Anders, Himanshu Kaul, Sanu Mathew, Vikram B. Suresh, Sudhir Satpathy, Amit Agarwal, Steven Hsu, Ram Krishnamurthy:
2.9TOPS/W Reconfigurable Dense/Sparse Matrix-Multiply Accelerator with Unified INT8/INTI6/FP16 Datapath in 14NM Tri-Gate CMOS. VLSI Circuits 2018: 39-40 - [c70]Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Vivek De:
An All-Digital Unified Static/Dynamic Entropy Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction for Secure Privacy-Preserving Mutual Authentication in IoT Mote Platforms. VLSI Circuits 2018: 169-170 - [c69]Sudhir Satpathy, Vikram B. Suresh, Sanu Mathew, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy:
220MV-900MV 794/584/754 GBPS/W Reconfigurable GF(24)2 AES/SMS4/Camellia Symmetric-Key Cipher Accelerator in 14NM Tri-Gate CMOS. VLSI Circuits 2018: 175-176 - [c68]Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Phil C. Knag, Ram K. Krishnamurthy:
A 4096-Neuron 1M-Synapse 3.8PJ/SOP Spiking Neural Network with On-Chip STDP Learning and Sparse Weights in 10NM FinFET CMOS. VLSI Circuits 2018: 255-256 - 2017
- [j33]Vivek De, Sriram R. Vangal, Ram Krishnamurthy:
Near Threshold Voltage (NTV) Computing: Computing in the Dark Silicon Era. IEEE Des. Test 34(2): 24-30 (2017) - [j32]Sudhir Satpathy, Sanu K. Mathew, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram K. Krishnamurthy, Vivek K. De:
A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS. IEEE J. Solid State Circuits 52(4): 940-949 (2017) - [c67]Shihui Yin, Shreyas K. Venkataramanaiah, Gregory K. Chen, Ram Krishnamurthy, Yu Cao, Chaitali Chakrabarti, Jae-sun Seo:
Algorithm and hardware design of discrete-time spiking neural networks based on back propagation with binary activations. BioCAS 2017: 1-5 - [c66]Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Ram K. Krishnamurthy:
Energy efficient and ultra low voltage security circuits for nanoscale CMOS technologies. CICC 2017: 1-4 - [c65]Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Ram Krishnamurthy:
Invited paper: Ultra-low energy security circuit primitives for IoT platforms. ISLPED 2017: 1-4 - [i1]Shihui Yin, Shreyas K. Venkataramanaiah, Gregory K. Chen, Ram Krishnamurthy, Yu Cao, Chaitali Chakrabarti, Jae-sun Seo:
Algorithm and Hardware Design of Discrete-Time Spiking Neural Networks Based on Back Propagation with Binary Activations. CoRR abs/1709.06206 (2017) - 2016
- [j31]Sanu K. Mathew, David Johnston, Sudhir Satpathy, Vikram B. Suresh, Paul Newman, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram K. Krishnamurthy:
µRNG: A 300-950 mV, 323 Gbps/W All-Digital Full-Entropy True Random Number Generator in 14 nm FinFET CMOS. IEEE J. Solid State Circuits 51(7): 1695-1704 (2016) - [c64]Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Mark A. Anders, Gregory K. Chen, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Vivek De:
A 305mV-850mV 400μW 45GSamples/J reconfigurable compressive sensing engine with early-termination for ultra-low energy target detection in 14nm tri-gate CMOS. A-SSCC 2016: 253-256 - [c63]Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Ram Krishnamurthy:
Ultra-low energy security circuits for IoT applications. ICCD 2016: 682-685 - [c62]Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Gregory K. Chen, Sudhir Satpathy, Steven Hsu, Amit Agarwal, Ram Krishnamurthy:
14.4 A 21.5M-query-vectors/s 3.37nJ/vector reconfigurable k-nearest-neighbor accelerator with adaptive precision in 14nm tri-gate CMOS. ISSCC 2016: 260-261 - [c61]Amit Agarwal, Steven Hsu, Mark A. Anders, Sanu Mathew, Gregory K. Chen, Himanshu Kaul, Sudhir Satpathy, Ram Krishnamurthy:
A 350mV-900mV 2.1GHz 0.011mm2 regular expression matching accelerator with aging-tolerant low-VMIN circuits in 14nm tri-gate CMOS. VLSI Circuits 2016: 1-2 - [c60]Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram Krishnamurthy, Vivek De:
A 4fJ/bit delay-hardened physically unclonable function circuit with selective bit destabilization in 14nm tri-gate CMOS. VLSI Circuits 2016: 1-2 - [c59]Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram Krishnamurthy:
250mV-950mV 1.1Tbps/W double-affine mapped Sbox based composite-field SMS4 encrypt/decrypt accelerator in 14nm tri-gate CMOS. VLSI Circuits 2016: 1-2 - 2015
- [j30]Gregory K. Chen, Mark A. Anders, Himanshu Kaul, Sudhir Satpathy, Sanu K. Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Vivek De, Shekhar Borkar:
A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS. IEEE J. Solid State Circuits 50(1): 59-67 (2015) - [j29]Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram Krishnamurthy:
340 mV-1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS. IEEE J. Solid State Circuits 50(4): 1048-1058 (2015) - [c58]Sanu Mathew, David Johnston, Paul Newman, Sudhir Satpathy, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Gregory K. Chen, Amit Agarwal, Steven Hsu, Ram Krishnamurthy:
μRNG: A 300-950mV 323Gbps/W all-digital full-entropy true random number generator in 14nm FinFET CMOS. ESSCIRC 2015: 116-119 - 2014
- [c57]Sudhir Satpathy, Sanu Mathew, Jiangtao Li, Patrick Koeberl, Mark A. Anders, Himanshu Kaul, Gregory K. Chen, Amit Agarwal, Steven Hsu, Ram Krishnamurthy:
13fJ/bit probing-resilient 250K PUF array with soft darkbit masking for 1.94% bit-error in 22nm tri-gate CMOS. ESSCIRC 2014: 239-242 - [c56]Gregory K. Chen, Mark A. Anders, Himanshu Kaul, Sudhir Satpathy, Sanu K. Mathew, Steven K. Hsu, Amit Agarwal, Ram K. Krishnamurthy, Shekhar Borkar, Vivek De:
16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS. ISSCC 2014: 276-277 - [c55]Sanu K. Mathew, Sudhir Satpathy, Mark A. Anders, Himanshu Kaul, Steven K. Hsu, Amit Agarwal, Gregory K. Chen, R. J. Parker, Ram K. Krishnamurthy, Vivek De:
16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS. ISSCC 2014: 278-279 - [c54]Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Himanshu Kaul, Mark A. Anders, Gregory K. Chen, Amit Agarwal, Steven Hsu, Ram Krishnamurthy:
340mV-1.1V, 289Gbps/W, 2090-gate NanoAES hardware accelerator with area-optimized encrypt/decrypt GF(24)2 polynomials in 22nm tri-gate CMOS. VLSIC 2014: 1-2 - 2013
- [j28]Steven Hsu, Amit Agarwal, Mark A. Anders, Sanu Mathew, Himanshu Kaul, Farhana Sheikh, Ram K. Krishnamurthy:
A 280 mV-to-1.1 V 256b Reconfigurable SIMD Vector Permutation Engine With 2-Dimensional Shuffle in 22 nm Tri-Gate CMOS. IEEE J. Solid State Circuits 48(1): 118-127 (2013) - [j27]Farhana Sheikh, Sanu Mathew, Mark A. Anders, Himanshu Kaul, Steven Hsu, Amit Agarwal, Ram K. Krishnamurthy, Shekhar Borkar:
A 2.05 GVertices/s 151 mW Lighting Accelerator for 3D Graphics Vertex and Pixel Shading in 32 nm CMOS. IEEE J. Solid State Circuits 48(1): 128-139 (2013) - [c53]Suresh Srinivasan, Ketan Bhudiya, Rajaraman Ramanarayanan, P. Sahit Babu, Tiju Jacob, Sanu Mathew, Ram Krishnamurthy, Vasantha Erraguntla:
Split-Path Fused Floating Point Multiply Accumulate (FPMAC). IEEE Symposium on Computer Arithmetic 2013: 17-24 - 2012
- [j26]Sanu Mathew, Suresh Srinivasan, Mark A. Anders, Himanshu Kaul, Steven Hsu, Farhana Sheikh, Amit Agarwal, Sudhir Satpathy, Ram Krishnamurthy:
2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors. IEEE J. Solid State Circuits 47(11): 2807-2821 (2012) - [c52]Himanshu Kaul, Mark A. Anders, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar:
Near-threshold voltage (NTV) design: opportunities and challenges. DAC 2012: 1153-1158 - [c51]Amit Agarwal, Steven Hsu, Sanu Mathew, Mark A. Anders, Himanshu Kaul, Farhana Sheikh, Ram Krishnamurthy:
A 260mV 468GOPS/W 256b 4-way to 32-way vector shifter with permute-assisted skip in 22nm tri-gate CMOS. ESSCIRC 2012: 177-180 - [c50]Steven Hsu, Amit Agarwal, Mark A. Anders, Sanu Mathew, Himanshu Kaul, Farhana Sheikh, Ram Krishnamurthy:
A 280mV-to-1.1V 256b reconfigurable SIMD vector permutation engine with 2-dimensional shuffle in 22nm CMOS. ISSCC 2012: 178-180 - [c49]Himanshu Kaul, Mark A. Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Farhana Sheikh, Ram Krishnamurthy, Shekhar Borkar:
A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS. ISSCC 2012: 182-184 - [c48]Farhana Sheikh, Sanu Mathew, Mark A. Anders, Himanshu Kaul, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar:
A 2.05GVertices/s 151mW lighting accelerator for 3D graphics vertex and pixel shading in 32nm CMOS. ISSCC 2012: 184-186 - [c47]Steven Hsu, Amit Agarwal, Mark A. Anders, Himanshu Kaul, Sanu Mathew, Farhana Sheikh, Ram Krishnamurthy, Shekhar Borkar:
A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS. VLSIC 2012: 118-119 - 2011
- [j25]Sanu Mathew, Farhana Sheikh, Michael E. Kounavis, Shay Gueron, Amit Agarwal, Steven Hsu, Himanshu Kaul, Mark A. Anders, Ram Krishnamurthy:
53 Gbps Native GF(2 4) 2 Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors. IEEE J. Solid State Circuits 46(4): 767-776 (2011) - [j24]Jae-sun Seo, Himanshu Kaul, Ram Krishnamurthy, Dennis Sylvester, David T. Blaauw:
A Robust Edge Encoding Technique for Energy-Efficient Multi-Cycle Interconnect. IEEE Trans. Very Large Scale Integr. Syst. 19(2): 264-273 (2011) - [c46]Ram Krishnamurthy, Sanu Mathew, Farhana Sheikh:
High-performance energy-efficient encryption in the sub-45nm CMOS Era. DAC 2011: 332 - [c45]Amit Agarwal, Steven Hsu, Sanu Mathew, Mark A. Anders, Himanshu Kaul, Farhana Sheikh, Ram Krishnamurthy:
A 128×128b high-speed wide-and match-line content addressable memory in 32nm CMOS. ESSCIRC 2011: 83-86 - [p1]Mark A. Anders, Himanshu Kaul, Ram K. Krishnamurthy, Shekhar Y. Borkar:
Hybrid Circuit/Packet Switched Network for Energy Efficient on-Chip Interconnections. Low Power Networks-on-Chip 2011: 3-20 - [e1]Andreas Koch, Ram Krishnamurthy, John McAllister, Roger F. Woods, Tarek A. El-Ghazawi:
Reconfigurable Computing: Architectures, Tools and Applications - 7th International Symposium, ARC 2011, Belfast, UK, March 23-25, 2011. Proceedings. Lecture Notes in Computer Science 6578, Springer 2011, ISBN 978-3-642-19474-0 [contents] - 2010
- [j23]Himanshu Kaul, Mark A. Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar:
A 300 mV 494GOPS/W Reconfigurable Dual-Supply 4-Way SIMD Vector Processing Accelerator in 45 nm CMOS. IEEE J. Solid State Circuits 45(1): 95-102 (2010) - [c44]Ram Krishnamurthy:
High-Performance Energy-Efficient Reconfigurable Accelerators/Co-processors for Tera-Scale Multi-core Microprocessors. ARC 2010: 1 - [c43]Sanu Mathew, Michael E. Kounavis, Farhana Sheikh, Steven Hsu, Amit Agarwal, Himanshu Kaul, Mark A. Anders, Frank L. Berry, Ram Krishnamurthy:
3GHz, 74mW 2-level Karatsuba 64b Galois field multiplier for public-key encryption acceleration in 45nm CMOS. ESSCIRC 2010: 198-201 - [c42]Rajaraman Ramanarayanan, Sanu Mathew, Farhana Sheikh, Suresh Srinivasan, Amit Agarwal, Steven Hsu, Himanshu Kaul, Mark A. Anders, Vasantha Erraguntla, Ram Krishnamurthy:
18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS. ESSCIRC 2010: 210-213 - [c41]Mark A. Anders, Himanshu Kaul, Steven Hsu, Amit Agarwal, Sanu Mathew, Farhana Sheikh, Ram Krishnamurthy, Shekhar Borkar:
A 4.1Tb/s bisection-bandwidth 560Gb/s/W streaming circuit-switched 8×8 mesh network-on-chip in 45nm CMOS. ISSCC 2010: 110-111 - [c40]Amit Agarwal, Sanu Mathew, Steven Hsu, Mark A. Anders, Himanshu Kaul, Farhana Sheikh, Rajaraman Ramanarayanan, Suresh Srinivasan, Ram Krishnamurthy, Shekhar Borkar:
A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media accelerators in 32nm CMOS. ISSCC 2010: 328-329 - [c39]Don Draper, Fabio Campi, Ram Krishnamurthy, Takashi Miyamori, Shannon Morton, Willy Sansen, Vladimir Stojanovic, John T. Stonick:
Signal and power integrity for SoCs. ISSCC 2010: 520
2000 – 2009
- 2009
- [j22]Donhee Ham, Hideto Hidaka, Ron Ho, Ram K. Krishnamurthy:
Introduction to the Special Issue on the 2008 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits 44(1): 3-6 (2009) - [j21]Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Steven Hsu, Amit Agarwal, Ram K. Krishnamurthy, Shekhar Borkar:
A 320 mV 56 μW 411 GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65 nm CMOS. IEEE J. Solid State Circuits 44(1): 107-114 (2009) - [c38]Himanshu Kaul, Mark A. Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar:
A 300mV 494GOPS/W reconfigurable dual-supply 4-Way SIMD vector processing accelerator in 45nm CMOS. ISSCC 2009: 260-261 - [c37]Suresh Srinivasan, Sanu Mathew, Vasantha Erraguntla, Ram Krishnamurthy:
A 4Gbps 0.57pJ/bit Process-Voltage-Temperature Variation Tolerant All-Digital True Random Number Generator in 45nm CMOS. VLSI Design 2009: 301-306 - 2008
- [j20]David Money Harris, Sreedhar Natarajan, Ram K. Krishnamurthy, Siva G. Narendra:
Introduction to the Special Issue on the 2007 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits 43(1): 3-5 (2008) - [j19]Mark A. Anders, Sanu K. Mathew, Steven Hsu, Ram K. Krishnamurthy, Shekhar Borkar:
A 1.9 Gb/s 358 mW 16-256 State Reconfigurable Viterbi Accelerator in 90 nm CMOS. IEEE J. Solid State Circuits 43(1): 214-222 (2008) - [j18]Shuvra S. Bhattacharyya, Jeffery C. Bier, Wanda K. Gass, Ram K. Krishnamurthy, Edward A. Lee, Konstantinos Konstantinides:
Advances in hardware design and implementation of signal processing systems [DSP Forum]. IEEE Signal Process. Mag. 25(6): 175-180 (2008) - [c36]Mark A. Anders, Himanshu Kaul, Martin Hansson, Ram Krishnamurthy, Shekhar Borkar:
A 2.9Tb/s 8W 64-core circuit-switched network-on-chip in 45nm CMOS. ESSCIRC 2008: 182-185 - [c35]Himanshu Kaul, Jae-sun Seo, Mark A. Anders, Dennis Sylvester, Ram Krishnamurthy:
A robust alternate repeater technique for high performance busses in the multi-core era. ISCAS 2008: 372-375 - [c34]Himanshu Kaul, Mark A. Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar:
A 320mV 56μW 411GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65nm CMOS. ISSCC 2008: 316-317 - [c33]Rajaraman Ramanarayanan, Sanu Mathew, Vasantha Erraguntla, Ram Krishnamurthy, Shay Gueron:
A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores. VLSI Design 2008: 273-278 - 2007
- [j17]Sapumal B. Wijeratne, Nanda Siddaiah, Sanu K. Mathew, Mark A. Anders, Ram K. Krishnamurthy, Jeremy Anderson, Matthew Ernest, Mark D. Nardin:
A 9-GHz 65-nm Intel® Pentium 4 Processor Integer Execution Unit. IEEE J. Solid State Circuits 42(1): 26-37 (2007) - [c32]Amit Agarwal, Nilanjan Banerjee, Steven K. Hsu, Ram K. Krishnamurthy, Kaushik Roy:
A 200mV to 1.2V, 4.4MHz to 6.3GHz, 48×42b 1R/1W programmable register file in 65nm CMOS. ESSCIRC 2007: 316-319 - [c31]Jae-sun Seo, Dennis Sylvester, David T. Blaauw, Himanshu Kaul, Ram Krishnamurthy:
A robust edge encoding technique for energy-efficient multi-cycle interconnect. ISLPED 2007: 68-73 - [c30]Toru Shimizu, Ram Krishnamurthy:
SE4 Automotive Signal Processing Technologies. ISSCC 2007: 148-149 - [c29]Mark A. Anders, Sanu Mathew, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar:
A 1.9Gb/s 358mW 16-to-256 State Reconfigurable Viterbi Accelerator in 90nm CMOS. ISSCC 2007: 256-600 - [c28]Sanu Mathew, David Money Harris, Mark A. Anders, Steven Hsu, Ram Krishnamurthy:
A 2.4GHz 256/1024-bit Encryption Accelerator reconfigurable Montgomery multiplier in 90nm CMOS. SoCC 2007: 25-28 - 2006
- [j16]Jan Van der Spiegel, Ram K. Krishnamurthy, Sreedhar Natarajan, Chih-Kong Ken Yang:
Introduction to the Special Issue on the 2005 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits 41(1): 3-6 (2006) - [j15]Steven K. Hsu, Sanu K. Mathew, Mark A. Anders, Bart R. Zeydel, Vojin G. Oklobdzija, Ram K. Krishnamurthy, Shekhar Y. Borkar:
A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS. IEEE J. Solid State Circuits 41(1): 256-264 (2006) - [j14]Chris H. Kim, Kaushik Roy, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar:
A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits. IEEE Trans. Very Large Scale Integr. Syst. 14(6): 646-649 (2006) - [c27]Sapumal B. Wijeratne, Nanda Siddaiah, Sanu Mathew, Mark A. Anders, Ram Krishnamurthy, Jeremy Anderson, Seung Hwang, Matthew Ernest, Mark D. Nardin:
A 9GHz 65nm Intel Pentium 4 Processor Integer Execution Core. ISSCC 2006: 353-365 - [c26]Steven K. Hsu, Amit Agarwal, Mark A. Anders, Sanu Mathew, Ram Krishnamurthy, Shekhar Borkar:
An 8.8GHz 198mW 16x64b 1R/1W variationtolerant register file in 65nm CMOS. ISSCC 2006: 1785-1797 - [c25]Vishak Venkatraman, Mark A. Anders, Himanshu Kaul, Wayne P. Burleson, Ram Krishnamurthy:
A Low-swing Signaling Circuit Technique for 65nm On-chip Interconnects. SoCC 2006: 289-292 - [c24]Amit Agarwal, Ram Krishnamurthy:
High-performance energy-efficient memory circuit technologies for sub-45nm technologies. SoCC 2006: 322 - 2005
- [j13]Sanu K. Mathew, Mark A. Anders, Brad Bloechel, Trang Nguyen, Ram K. Krishnamurthy, Shekhar Borkar:
A 4-GHz 300-mW 64-bit integer execution ALU with dual supply voltages in 90-nm CMOS. IEEE J. Solid State Circuits 40(1): 44-51 (2005) - [j12]Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy:
Designing leakage tolerant, low power wide-OR dominos for sub-130nm CMOS technologies. Microelectron. J. 36(9): 801-809 (2005) - [j11]Vojin G. Oklobdzija, Bart R. Zeydel, Hoang Q. Dao, Sanu Mathew, Ram Krishnamurthy:
Comparison of high-performance VLSI adders in the energy-delay space. IEEE Trans. Very Large Scale Integr. Syst. 13(6): 754-758 (2005) - [j10]Himanshu Kaul, Dennis Sylvester, Mark A. Anders, Ram Krishnamurthy:
Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses. IEEE Trans. Very Large Scale Integr. Syst. 13(11): 1225-1238 (2005) - [c23]David Money Harris, Ram Krishnamurthy, Mark A. Anders, Sanu Mathew, Steven Hsu:
An Improved Unified Scalable Radix-2 Montgomery Multiplier. IEEE Symposium on Computer Arithmetic 2005: 172-178 - [c22]Steven Hsu, Vishak Venkatraman, Sanu Mathew, Himanshu Kaul, Mark A. Anders, Saurabh Dighe, Wayne P. Burleson, Ram Krishnamurthy:
A 2GHz 13.6mW 12 × 9b multiplier for energy efficient FFT accelerators. ESSCIRC 2005: 199-202 - [c21]Chris H. Kim, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar, Kaushik Roy:
Self Calibrating Circuit Design for Variation Tolerant VLSI Systems. IOLTS 2005: 100-105 - [c20]Steven Hsu, Amit Agarwal, Kaushik Roy, Ram Krishnamurthy, Shekhar Borkar:
An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS. ISLPED 2005: 103-106 - 2004
- [c19]Peter Caputa, Mark A. Anders, Christer Svensson, Ram K. Krishnamurthy, Shekhar Borkar:
A low-swing single-ended L1 cache bus technique for sub-90nm technologies. ESSCIRC 2004: 475-477 - [c18]Himanshu Kaul, Dennis Sylvester, Mark A. Anders, Ram Krishnamurthy:
Spatial encoding circuit techniques for peak power reduction of on-chip high-performance buses. ISLPED 2004: 194-199 - [c17]Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy:
A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies. ISLPED 2004: 248-251 - [c16]Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy:
Leakage Control Techniques for Designing Robust, Low Power Wide-OR Domino Logic for sub-130 nm CMOS Technologies. ISQED 2004: 415-420 - [c15]Amit Agarwal, Kaushik Roy, Ram K. Krishnamurthy:
A leakage-tolerant low-leakage register file with conditional sleep transistor. SoCC 2004: 241-244 - 2003
- [j9]Sanu Mathew, Mark A. Anders, Ram K. Krishnamurthy, Shekhar Borkar:
A 4-GHz 130-nm address generation unit with 32-bit sparse-tree adder core. IEEE J. Solid State Circuits 38(5): 689-695 (2003) - [j8]Mark A. Anders, Nivruti Rai, Ram K. Krishnamurthy, Shekhar Borkar:
A transition-encoded dynamic bus technique for high-performance interconnects. IEEE J. Solid State Circuits 38(5): 709-714 (2003) - [j7]Steven Hsu, Atila Alvandpour, Sanu Mathew, Shih-Lien Lu, Ram K. Krishnamurthy, Shekhar Borkar:
A 4.5-GHz 130-nm 32-KB L0 cache with a leakage-tolerant self reverse-bias bitline scheme. IEEE J. Solid State Circuits 38(5): 755-761 (2003) - [c14]Vojin G. Oklobdzija, Bart R. Zeydel, Hoang Q. Dao, Sanu Mathew, Ram Krishnamurthy:
Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders. IEEE Symposium on Computer Arithmetic 2003: 272-279 - [c13]Vojin G. Oklobdzija, Ram Krishnamurthy:
Tutorial: Design of Power Efficient VLSI Arithmetic: Speed and Power Trade-Offs. IEEE Symposium on Computer Arithmetic 2003: 280 - [c12]Atila Alvandpour, Dinesh Somasekhar, Ram Krishnamurthy, Vivek De, Shekhar Borkar, Christer Svensson:
Bitline leakage equalization for sub-100nm caches. ESSCIRC 2003: 401-404 - [c11]Manoj Sinha, Steven Hsu, Atila Alvandpour, Wayne P. Burleson, Ram Krishnamurthy, Shekhar Borkar:
Low voltage sensing techniques and secondary design issues for sub-90nm caches. ESSCIRC 2003: 413-416 - [c10]Bhaskar Chatterjee, Manoj Sachdev, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar:
Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies. ISLPED 2003: 122-127 - 2002
- [j6]Ram K. Krishnamurthy, Atila Alvandpour, Ganesh Balamurugan, Naresh R. Shanbhag, Krishnamurthy Soumyanath, Shekhar Y. Borkar:
A 130-nm 6-GHz 256 × 32 bit leakage-tolerant register file. IEEE J. Solid State Circuits 37(5): 624-632 (2002) - [j5]Atila Alvandpour, Ram K. Krishnamurthy, Krishnamurthy Soumyanath, Shekhar Y. Borkar:
A sub-130-nm conditional keeper technique. IEEE J. Solid State Circuits 37(5): 633-638 (2002) - [j4]Sriram R. Vangal, Mark A. Anders, Nitin Borkar, Erik Seligman, Venkatesh Govindarajulu, Vasantha Erraguntla, Howard Wilson, Amaresh Pangal, Venkat Veeramachaneni, James W. Tschanz, Yibin Ye, Dinesh Somasekhar, Bradley A. Bloechel, Gregory E. Dermer, Ram K. Krishnamurthy, Krishnamurthy Soumyanath, Sanu Mathew, Siva G. Narendra, Mircea R. Stan, Scott Thompson, Vivek De, Shekhar Borkar:
5-GHz 32-bit integer execution core in 130-nm dual-VT CMOS. IEEE J. Solid State Circuits 37(11): 1421-1432 (2002) - [c9]Atila Alvandpour, Ram Krishnamurthy, Shekhar Borkar, A. Rahman, Clair Webb:
A burn-in tolerant dynamic circuit technique. CICC 2002: 81-84 - [c8]Ram K. Krishnamurthy, Atila Alvandpour, Vivek De, Shekhar Borkar:
High-performance and low-power challenges for sub-70 nm microprocessor circuits. CICC 2002: 125-128 - [c7]Steven Hsu, Shih-Lien Lu, Shih-Chang Lai, Ram Krishnamurthy, Konrad Lai:
Dynamic addressing memory arrays with physical locality. MICRO 2002: 161-170 - 2001
- [j3]Sanu K. Mathew, Ram K. Krishnamurthy, Mark A. Anders, Rafael Rios, Kaizad R. Mistry, Krishnamurthy Soumyanath:
Sub-500-ps 64-b ALUs in 0.18-μm SOI/bulk CMOS: design and scaling trends. IEEE J. Solid State Circuits 36(11): 1636-1646 (2001) - [c6]Ram Krishnamurthy, Mark A. Anders, Krishnamurthy Soumyanath, Shekhar Borkar:
Leakage control and tolerance challenges for sub-0.1µm microprocessor circuits. ACM Great Lakes Symposium on VLSI 2001: 43-44 - [c5]Atila Alvandpour, Ram Krishnamurthy, Krishnamurthy Soumyanath, Shekhar Borkar:
A low-leakage dynamic multi-ported register file in 0.13mm CMOS. ISLPED 2001: 68-71
1990 – 1999
- 1998
- [c4]Ram Krishnamurthy, Herman Schmit, L. Richard Carley:
A low-power 16-bit multiplier-accumulator using series-regulated mixed swing techniques. CICC 1998: 499-502 - [c3]L. Richard Carley, Akshay Aggarwal, Ram K. Krishnamurthy:
Decreasing low-voltage manufacturing-induced delay variations with adaptive mixed-voltage-swing circuits. ISLPED 1998: 106-108 - 1997
- [j2]Ram K. Krishnamurthy, L. Richard Carley:
Exploring the design space of mixed swing quadrail for low-power digital circuits. IEEE Trans. Very Large Scale Integr. Syst. 5(4): 388-400 (1997) - 1996
- [j1]Venu Govindaraju, Ram K. Krishnamurthy:
Holistic handwritten word recognition using temporal features derived from off-line images. Pattern Recognit. Lett. 17(5): 537-540 (1996) - [c2]Ram K. Krishnamurthy, Ihor Lys, L. Richard Carley:
Static power driven voltage scaling and delay driven buffer sizing in mixed swing QuadRail for sub-1V I/O swings. ISLPED 1996: 381-386 - 1995
- [c1]Ram K. Krishnamurthy, Ramalingam Sridhar:
A CMOS wave-pipelined image processor for real-time morphology . ICCD 1995: 638-643
Coauthor Index
[c95] [c93] [j38] [j37] [j36] [c91] [c90] [c89] [c88] [c87] [j34] [c85] [c84] [c83] [c79] [c78] [c77] [c76] [c75] [c74] [c72] [c71] [c70] [c69] [j32] [j31] [c64] [c62] [c61] [c60] [c59] [j30] [j29] [c58] [c57] [c56] [c55] [c54] [j28] [j27] [j26] [c52] [c51] [c50] [c49] [c48] [c47] [j25] [c45] [j23] [c43] [c42] [c41] [c40] [j21] [c38] [c34] [c32] [c26] [c24] [c20] [c15]
[c95] [c93] [j38] [j36] [c91] [c90] [c89] [c88] [c87] [j34] [c86] [c85] [c84] [c83] [c79] [c78] [c77] [c76] [c75] [c74] [c72] [c71] [c70] [c69] [j32] [j31] [c64] [c62] [c61] [c60] [c59] [j30] [j29] [c58] [c57] [c56] [c55] [c54] [j28] [j27] [j26] [c52] [c51] [c50] [c49] [c48] [c47] [j25] [c45] [p1] [j23] [c43] [c42] [c41] [c40] [j21] [c38] [j19] [c36] [c35] [c34] [j17] [c29] [c28] [j15] [c27] [c26] [c25] [j13] [j10] [c23] [c22] [c19] [c18] [j9] [j8] [j4] [j3] [c6]
Shekhar Borkar
aka: Shekhar Y. Borkar
aka: Shekhar Y. Borkar
Vivek De
aka: Vivek K. De
aka: Vivek K. De
Steven Hsu
aka: Steven K. Hsu
aka: Steven K. Hsu
[c95] [c93] [j38] [j37] [j36] [c91] [c90] [c89] [c88] [c87] [j34] [c85] [c84] [c83] [c79] [c78] [c77] [c76] [c75] [c74] [c72] [c71] [c70] [c69] [j32] [j31] [c64] [c62] [c61] [c60] [c59] [j30] [j29] [c58] [c57] [c56] [c55] [c54] [j28] [j27] [j26] [c52] [c51] [c50] [c49] [c48] [c47] [j25] [c45] [j23] [c43] [c42] [c41] [c40] [j21] [c38] [j19] [c34] [c32] [c29] [c28] [j15] [j14] [c26] [c23] [c22] [c21] [c20] [j7] [c11] [c10] [c7]
[j38] [j36] [c91] [c90] [c89] [c88] [c87] [j34] [c86] [c85] [c84] [c83] [c79] [c78] [c77] [c76] [c75] [c74] [c72] [c71] [c70] [c69] [j32] [j31] [c64] [c62] [c61] [c60] [c59] [j30] [j29] [c58] [c57] [c56] [c55] [c54] [j28] [j27] [j26] [c52] [c51] [c50] [c49] [c48] [c47] [j25] [j24] [c45] [p1] [j23] [c43] [c42] [c41] [c40] [j21] [c38] [c36] [c35] [c34] [c31] [c25] [j10] [c22] [c18]
Sanu Mathew
aka: Sanu K. Mathew
aka: Sanu K. Mathew
[j36] [c91] [c90] [c89] [j34] [c86] [c85] [c84] [c83] [c79] [c78] [c77] [c76] [c75] [c74] [c73] [c72] [c71] [c70] [c69] [j32] [c66] [c65] [j31] [c64] [c63] [c62] [c61] [c60] [c59] [j30] [j29] [c58] [c57] [c56] [c55] [c54] [j28] [j27] [c53] [j26] [c51] [c50] [c49] [c48] [c47] [j25] [c46] [c45] [j23] [c43] [c42] [c41] [c40] [j21] [c38] [c37] [j19] [c34] [c33] [j17] [c29] [c28] [j15] [c27] [c26] [j13] [j11] [c23] [c22] [j9] [j7] [c14] [j4] [j3]
Huseyin Ekin Sumbul
aka: Huseyin Sumbul
aka: Huseyin Sumbul
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