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Semantic ScholarTakayuki Onishi
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2010 – today
- 2019
[c12]Ken Nakamura, Yuya Omori, Daisuke Kobayashi, Tatsuya Osawa, Takayuki Onishi, Koyo Nitta, Hiroe Iwasaki, Atsushi Shimizu:
Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture. COOL CHIPS 2019: 1-3- [c11]Satoshi Suzuki, Motohiro Takagi, Kazuya Hayase, Takayuki Onishi, Atsushi Shimizu:
Image Pre-Transformation for Recognition-Aware Image Compression. ICIP 2019: 2686-2690 - [c10]Yasuhiro Mochida, Takayuki Nakachi, Takahiro Yamaguchi, Takayuki Onishi, Ken Nakamura:
An MMT Module for 4K/120fps Temporally Scalable Video. ISCAS 2019: 1-5 - [c9]Takayuki Onishi, Yuya Omori, Ken Nakamura, Hiroe Iwasaki, Atsushi Shimizu:
A Low Power Motion Estimation Engine with Adaptive Bit-Shifted SAD Calculation. ISCAS 2019: 1-5 - 2018
- [j8]Daisuke Kobayashi
, Ken Nakamura, Takayuki Onishi, Hiroe Iwasaki, Atsushi Shimizu:
A 4K/60p HEVC Real-Time Encoding System With High Quality HDR Color Representations. IEEE Trans. Consumer Electronics 64(4): 433-441 (2018) - [j7]Yuya Omori, Takayuki Onishi, Hiroe Iwasaki, Atsushi Shimizu:
A 120 fps High Frame Rate Real-time HEVC Video Encoder with Parallel Configuration Scalable to 4K. IEEE Trans. Multi-Scale Computing Systems 4(4): 491-499 (2018) - [j6]Takayuki Onishi, Takashi Sano, Yukikuni Nishida, Kazuya Yokohari, Ken Nakamura, Koyo Nitta, Kimiko Kawashima, Jun Okamoto, Naoki Ono, Atsushi Sagata, Hiroe Iwasaki, Mitsuo Ikeda, Atsushi Shimizu:
A Single-Chip 4K 60-fps 4: 2: 2 HEVC Video Encoder LSI Employing Efficient Motion Estimation and Mode Decision Framework With Scalability to 8K. IEEE Trans. VLSI Syst. 26(10): 1930-1938 (2018) - [c8]Daisuke Kobayashi, Ken Nakamura, Takayuki Onishi, Yasuyuki Nakajima, Hiroe Iwasaki, Mitsuo Ikeda, Atsushi Shimizu:
An HEVC real-time encoding system with high quality HDR color representations. ICCE 2018: 1-2 - 2017
- [c7]Yuya Omori, Takayuki Onishi, Hiroe Iwasaki, Atsushi Shimizu:
A 120 fps high frame rate real-time HEVC video encoder with parallel configuration scalable to 4K. COOL Chips 2017: 1-3 - 2015
- [c6]Hiroe Iwasaki, Takayuki Onishi, Ken Nakamura, Koyo Nitta, Takashi Sano, Yukikuni Nishida, Kazuya Yokohari, Jia Su, Naoki Ono, Ritsu Kusaba, Atsushi Sagata, Mitsuo Ikeda, Atsushi Shimizu:
Professional H.265/HEVC encoder LSI toward high-quality 4K/8K broadcast infrastructure. Hot Chips Symposium 2015: 1-24 - [c5]Takayuki Onishi, Takashi Sano, Yukikuni Nishida, Kazuya Yokohari, Jia Su, Ken Nakamura, Koyo Nitta, Kimiko Kawashima, Jun Okamoto, Naoki Ono, Ritsu Kusaba, Atsushi Sagata, Hiroe Iwasaki, Mitsuo Ikeda, Atsushi Shimizu:
Single-chip 4K 60fps 4: 2: 2 HEVC video encoder LSI with 8K scalability. VLSIC 2015: 54- - 2012
- [j5]Koyo Nitta, Hiroe Iwasaki, Takayuki Onishi, Takashi Sano, Atsushi Sagata, Yasuyuki Nakajima, Minoru Inamori, Ryuichi Tanida, Atsushi Shimizu, Ken Nakamura, Mitsuo Ikeda, Jiro Naganuma:
An H.264/AVC High422 Profile and MPEG-2 422 Profile Encoder LSI for HDTV Broadcasting Infrastructures. IEICE Transactions 95-C(4): 432-440 (2012) - [c4]Mitsuo Ikeda, Takayuki Onishi, Takashi Sano, Atsushi Sagata, Hiroe Iwasaki, Yasuyuki Nakajima, Koyo Nitta, Yasuko Takahashi, Kazuya Yokohari, Daisuke Kobayashi, Kazuto Kamikura, Hirohisa Jozawa:
MVC real-time video encoder for full-HDTV 3D video. ICCE 2012: 166-167
2000 – 2009
- 2008
- [j4]Takayuki Onishi, Ken Nakamura, Takeshi Yoshitome, Jiro Naganuma:
A Distributed Stream Multiplexing Architecture for Multi-Chip Configuration beyond HDTV. IEICE Transactions 91-D(12): 2862-2867 (2008) - [c3]Takayuki Onishi, Takashi Sano, Koyo Nitta, Mitsuo Ikeda, Jiro Naganuma:
Multi-reference and multi-block-size motion estimation with flexible mode selection for professional 4: 2: 2 H.264/AVC encoder LSI. ISCAS 2008: 800-803 - 2007
- [j3]Hiroe Iwasaki, Jiro Naganuma, Koyo Nitta, Ken Nakamura, Takeshi Yoshitome, Mitsuo Ogura, Yasuyuki Nakajima, Yutaka Tashiro, Takayuki Onishi, Mitsuo Ikeda, Toshihiro Minami, Makoto Endo, Yoshiyuki Yashima:
Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Configuration for Large Scale Processing Beyond HDTV Level. IEEE Trans. VLSI Syst. 15(9): 1055-1059 (2007) - 2006
- [j2]Takayuki Onishi, Mitsuo Ikeda, Jiro Naganuma, Makoto Endo, Yoshiyuki Yashima:
Highly accurate de-jittering scheme for broadcast quality video transmission. Systems and Computers in Japan 37(10): 81-88 (2006) - 2005
- [j1]Minoru Inamori, Hiroe Iwasaki, Takayuki Onishi, Mitsuo Ikeda, Jiro Naganuma, Yoshiyuki Yashima:
New set-top box for interactive visual communication of home entertainment using MPEG-2 full-duplex CODEC LSI. IEEE Trans. Consumer Electronics 51(2): 640-641 (2005) - 2004
- [c2]Takayuki Onishi, Mitsuo Ikeda, Jiro Naganuma, Makoto Endo, Yoshiyuki Yashima:
A distributed TS-MUX architecture for multi-chip extension beyond the HDTV level. ISCAS (2) 2004: 261-264 - 2003
- [c1]Hiroe Iwasaki, Jiro Naganuma, Koyo Nitta, Ken Nakamura, Takeshi Yoshitome, Mitsuo Ogura, Yasuyuki Nakajima, Yutaka Tashiro, Takayuki Onishi, Mitsuo Ikeda, Makoto Endo:
Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level. DATE 2003: 20002-20007
Coauthor Index
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