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Semantic ScholarNidhal Selmane
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2010 – today
- 2011
[j1]Nidhal Selmane, Shivam Bhasin, Sylvain Guilley, Jean-Luc Danger:
Security evaluation of application-specific integrated circuits and field programmable gate arrays against setup time violation attacks. IET Information Security 5(4): 181-190 (2011)- [c9]Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Nidhal Selmane, Denis Réal:
Performance evaluation of protocols resilient to physical attacks. HOST 2011: 51-56 - 2010
- [b1]Nidhal Selmane:
Global and local Fault attacks on AES cryptoprocessor : Implementation and Countermeasures. (Attaques en fautes globales et locales sur les cryptoprocesseurs AES : mise en œuvre et contremesures). Télécom ParisTech, France, 2010 - [c8]Shivam Bhasin, Sylvain Guilley, Florent Flament, Nidhal Selmane, Jean-Luc Danger:
Countering early evaluation: an approach towards robust dual-rail precharge logic. WESS 2010: 6 - [c7]Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Nidhal Selmane:
Fault Injection Resilience. FDTC 2010: 51-65
2000 – 2009
- 2009
- [c6]Nidhal Selmane, Shivam Bhasin, Sylvain Guilley, Tarik Graba, Jean-Luc Danger:
WDDL is Protected against Setup Time Violation Attacks. FDTC 2009: 73-83 - [c5]Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Nidhal Selmane:
Security Evaluation of Different AES Implementations Against Practical Setup Time Violation Attacks in FPGAs. HOST 2009: 15-21 - [c4]Shivam Bhasin, Jean-Luc Danger, Florent Flament, Tarik Graba, Sylvain Guilley, Yves Mathieu, Maxime Nassar, Laurent Sauvage, Nidhal Selmane:
Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow. ReConFig 2009: 213-218 - 2008
- [c3]Nidhal Selmane, Sylvain Guilley, Jean-Luc Danger:
Practical Setup Time Violation Attacks on AES. EDCC 2008: 91-96 - [c2]Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Nidhal Selmane, Renaud Pacalet:
Silicon-level Solutions to Counteract Passive and Active Attacks. FDTC 2008: 3-17 - [c1]Farouk Khelil, Mohamed Hamdi, Sylvain Guilley, Jean-Luc Danger, Nidhal Selmane:
Fault Analysis Attack on an FPGA AES Implementation. NTMS 2008: 1-5
Coauthor Index
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