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ORCIDChauchin Su
Person information
- affiliation: National Chiao Tung University, Hsinchu, Taiwan
- affiliation (former): National Central University, Chungli, Taiwan
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2010 – 2019
- 2019
[c49]Ting-You Lin
, Chauchin Su, Chung-Chih Hung, Karuna Nidhi, Chily Tu, Shao-Chang Huang:
Package and Chip Accelerated Aging Methods for Power MOSFET Reliability Evaluation. DATE 2019: 1661-1666- 2017
- [j31]Ting-You Lin, Yingchieh Ho, Chauchin Su:
LDMOS Channel Thermometer Based on a Thermal Resistance Sensor for Balancing Temperature in Monolithic Power ICs. Sensors 17(6): 1397 (2017) - 2016
- [c48]Yuhwai Tseng, Ting-You Lin, Songwen Yau, Yingchieh Ho, Chauchin Su:
A 0.5V/22 μW low power transceiver IC for use in ESC intra-body communication system. ISOCC 2016: 71-72 - 2014
- [j30]Shu-Yu Hsu, Yingchieh Ho, Po-Yao Chang, Chauchin Su, Chen-Yi Lee:
A 48.6-to-105.2 µW Machine Learning Assisted Cardiac Sensor SoC for Mobile Healthcare Applications. IEEE J. Solid State Circuits 49(4): 801-811 (2014) - [c47]Yingchieh Ho, Chou-Ming Kuo, Chauchin Su:
A low-power analog-to-digital converter with digitalized amplifier for PAM systems. MWSCAS 2014: 109-112 - 2013
- [j29]Yingchieh Ho, Yu-Sheng Yang, Chiachi Chang, Chauchin Su:
A Near-Threshold 480 MHz 78 µW All-Digital PLL With a Bootstrapped DCO. IEEE J. Solid State Circuits 48(11): 2805-2814 (2013) - 2012
- [j28]Yingchieh Ho, Hung-Kai Chen, Chauchin Su:
Energy-Effective Sub-Threshold Interconnect Design Using High-Boosting Predrivers. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(2): 307-313 (2012) - [j27]Hung-Kai Chen, Yingchieh Ho, Chauchin Su:
Cumulative Differential Nonlinearity Testing of ADCs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(10): 1768-1775 (2012) - [j26]Yingchieh Ho, Chauchin Su:
A 0.1-0.3 V 40-123 fJ/bit/ch On-Chip Data Link With ISI-Suppressed Bootstrapped Repeaters. IEEE J. Solid State Circuits 47(5): 1242-1251 (2012) - [j25]Yuhwai Tseng, Yingchieh Ho, Shuoting Kao, Chauchin Su:
A 0.09 µW Low Power Front-End Biopotential Amplifier for Biosignal Recording. IEEE Trans. Biomed. Circuits Syst. 6(5): 508-516 (2012) - [j24]Yingchieh Ho, Chiachi Chang, Chauchin Su:
Design of a Subthreshold-Supply Bootstrapped CMOS Inverter Based on an Active Leakage-Current Reduction Technique. IEEE Trans. Circuits Syst. II Express Briefs 59-II(1): 55-59 (2012) - [c46]Shu-Yu Hsu, Yingchieh Ho, Yuhwai Tseng, Ting-You Lin, Po-Yao Chang, Jen-Wei Lee, Ju-Hung Hsiao, Siou-Ming Chuang, Tze-Zheng Yang, Po-Chun Liu, Ten-Fang Yang, Ray-Jade Chen, Chauchin Su, Chen-Yi Lee:
A sub-100µW multi-functional cardiac signal processor for mobile healthcare applications. VLSIC 2012: 156-157 - 2011
- [c45]Yingchieh Ho, Yu-Sheng Yang, Chauchin Su:
A 0.2-0.6 V ring oscillator design using bootstrap technique. A-SSCC 2011: 333-336 - 2010
- [j23]Yuhwai Tseng, Chauchin Su, Chien-Nan Jimmy Liu:
Measuring the Transmission Characteristic of the Human Body in an Electrostatic-Coupling Intra Body Communication System Using a Square Test Stimulus. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(3): 664-668 (2010) - [j22]Yuhwai Tseng, Chauchin Su, Chien-Nan Jimmy Liu:
Measurement and Evaluation of the Bioelectrical Impedance of the Human Body by Deconvolution of a Square Wave. IEICE Trans. Inf. Syst. 93-D(6): 1656-1660 (2010) - [j21]Jen-Chien Hsu, Chauchin Su:
Timing Jitter and Modulation Profile Extraction for Spread-Spectrum Clocks. IEEE Trans. Instrum. Meas. 59(4): 847-856 (2010) - [c44]Hung-Wen Lin, Yingchieh Ho, YingLin Fa, Chauchin Su:
A 5Gb/s pulse signaling interface for low power on-chip data communication. ISCAS 2010: 201-204
2000 – 2009
- 2009
- [j20]Yuhwai Tseng, Chauchin Su, Chien-Nan Jimmy Liu:
Analysis and Design of Wide-Band Digital Transmission in an Electrostatic-Coupling Intra-Body Communication System. IEICE Trans. Commun. 92-B(11): 3557-3563 (2009) - [j19]Hungwen Lu, Chauchin Su, Chien-Nan Jimmy Liu:
A Tree-Topology Multiplexer for Multiphase Clock System. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(1): 124-131 (2009) - [j18]Hungwen Lu, Hsin-Wen Wang, Chauchin Su, Chien-Nan Jimmy Liu:
Design of an All-Digital LVDS Driver. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(8): 1635-1644 (2009) - [j17]Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen:
A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus. IEEE Trans. Very Large Scale Integr. Syst. 17(2): 306-311 (2009) - 2008
- [j16]Hungwen Lu, Chauchin Su, Chien-Nan Jimmy Liu:
A Scalable Digitalized Buffer for Gigabit I/O. IEEE Trans. Circuits Syst. II Express Briefs 55-II(10): 1026-1030 (2008) - [j15]Chih-Hu Wang, Bor-Sen Chen, Bore-Kuen Lee, Tsu-Tian Lee, Chien-Nan Jimmy Liu, Chauchin Su:
Long-Range Prediction for Real-Time MPEG Video Traffic: An Hinfty Filter Approach. IEEE Trans. Circuits Syst. Video Technol. 18(12): 1771-1775 (2008) - [j14]Jen-Chien Hsu, Chauchin Su:
BIST for Measuring Clock Jitter of Charge-Pump Phase-Locked Loops. IEEE Trans. Instrum. Meas. 57(2): 276-285 (2008) - [c43]Hungwen Lu, Chauchin Su, Chien-Nan Liu:
A scalable digitalized buffer for gigabit I/O. CICC 2008: 241-244 - 2007
- [j13]Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen:
IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection. J. Electron. Test. 23(4): 341-355 (2007) - [j12]Katherine Shu-Min Li, Yao-Wen Chang, Chung-Len Lee, Chauchin Su, Jwu E. Chen:
Multilevel Full-Chip Routing With Testability and Yield Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(9): 1625-1636 (2007) - [c42]Hung-Kai Chen, Chauchin Su:
A Test and Diagnosis Methodology for RF Transceivers. ATS 2007: 135-138 - 2006
- [j11]Wenliang Tseng, Chien-Nan Jimmy Liu, Chauchin Su:
Passive Reduced-Order Macro-Modeling for Linear Time-Delay Interconnect Systems. IEICE Trans. Electron. 89-C(11): 1713-1718 (2006) - [j10]Katherine Shu-Min Li, Chauchin Su, Yao-Wen Chang, Chung-Len Lee, Jwu E. Chen:
IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11): 2513-2525 (2006) - [c41]Katherine Shu-Min Li, Yao-Wen Chang, Chauchin Su, Chung-Len Lee, Jwu E. Chen:
IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults. ASP-DAC 2006: 366-371 - [c40]Maohsuan Chou, Jen-Chien Hsu, Chauchin Su:
A Digital BIST Methodology for Spread Spectrum Clock Generators. ATS 2006: 251-254 - [c39]Chih-Hu Wang, Bore-Kuen Lee, Wei-Hang Tseng, Chung-Hsi Fu, Chauchin Su, Chien-Nan Jimmy Liu:
Estimation of Loss Coefficients of Nonlinear Rubber Using Iterative H∞ Filter. SMC 2006: 960-965 - 2005
- [c38]Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen:
Oscillation ring based interconnect test scheme for SOC. ASP-DAC 2005: 184-187 - [c37]Katherine Shu-Min Li, Chung-Len Lee, Tagin Jiang, Chauchin Su, Jwu E. Chen:
Finite State Machine Synthesis for At-Speed Oscillation Testability. Asian Test Symposium 2005: 360-365 - [c36]Wei-Ta Chen, Jen-Chien Hsu, Hong-Wen Lune, Chauchin Su:
A spread spectrum clock generator for SATA-II. ISCAS (3) 2005: 2643-2646 - [c35]Katherine Shu-Min Li, Chung-Len Lee, Yao-Wen Chang, Chauchin Su, Jwu E. Chen:
Multilevel full-chip routing with testability and yield enhancement. SLIP 2005: 29-36 - 2004
- [c34]Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen:
A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-Micron VLSI. Asian Test Symposium 2004: 145-150 - 2003
- [c33]Chauchin Su, Wei-Juo Wang, Chih-Hu Wang, I. S. Tseng:
A novel LCD driver testing technique using logic test channels. ASP-DAC 2003: 657-662 - [c32]Chauchin Su, Chih-Hu Wang, Wei-Juo Wang, I. S. Tseng:
1149.4 Based On-Line Quiescent State Monitoring Technique. VTS 2003: 197-202 - 2002
- [j9]Kuen-Jong Lee, Chau-Chin Su:
Guest Editorial. J. Electron. Test. 18(1): 15-16 (2002) - [j8]Chih-Wen Lu, Chung-Len Lee, Chauchin Su, Jwu-E Chen:
Analysis of Application of the IDDQ Technique to the Deep Sub-Micron VLSI Testing. J. Electron. Test. 18(1): 89-97 (2002) - [c31]Hung-Kai Chen, Chih-Hu Wang, Chau-Chin Su:
A Self Calibrated ADC BIST Methodology. VTS 2002: 117-122 - 2001
- [j7]Jun-Weir Lin, Chung-Len Lee, Chauchin Su, Jwu E. Chen:
Fault Diagnosis for Linear Analog Circuits. J. Electron. Test. 17(6): 483-494 (2001) - [j6]Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou:
Intrinsic response for analog module testing using an analog testability bus. ACM Trans. Design Autom. Electr. Syst. 6(2): 226-243 (2001) - [c30]Chauchin Su, Shih-Ching Hsiao, Hau-Zen Zhau, Chung-Len Lee:
A computer aided engineering system for memory BIST. ASP-DAC 2001: 492-495 - [c29]Chauchin Su, Wenliang Tseng:
Configuration free SoC interconnect BIST methodology. ITC 2001: 1033-1038 - [c28]Yue-Tsang Chen, Chauchin Su:
Test Waveform Shaping in Mixed Signal Test Bus by Pre-Equalization. VTS 2001: 260-265 - 2000
- [j5]Yeong-Jar Chang, Chung-Len Lee, Jwu E. Chen, Chauchin Su:
A Behavior-Level Fault Model for the Closed-Loop Operational Amplifier. J. Inf. Sci. Eng. 16(5): 751-766 (2000) - [j4]Chauchin Su, Yue-Tsang Chen, Shenshung Chiang:
Impulse Response Fault Model and Fault Extraction for Functional Level Analog Circuit Diagnosis. J. Inf. Sci. Eng. 16(5): 767-781 (2000) - [j3]Chauchin Su, Yue-Tsang Chen:
Intrinsic response extraction for the removal of the parasiticeffects in analog test buses. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(4): 437-445 (2000) - [c27]Jun-Weir Lin, Chung-Len Lee, Chauchin Su, Jwu E. Chen:
Fault diagnosis for linear analog circuits. Asian Test Symposium 2000: 25-30 - [c26]Yin-Chao Huang, Chung-Len Lee, Jun-Weir Lin, Jwu E. Chen, Chauchin Su:
A methodology for fault model development for hierarchical linear systems. Asian Test Symposium 2000: 90-95 - [c25]Chih-Wen Lu, Chauchin Su, Chung-Len Lee, Jwu E. Chen:
Is IDDQ testing not applicable for deep submicron VLSI in year 2011? Asian Test Symposium 2000: 338-343 - [c24]Chauchin Su, Yue-Tsang Chen, Mu-Jeng Huang, Gen-Nan Chen, Chung-Len Lee:
All Digital Built-in Delay and Crosstalk Measurement for On-Chip Buses. DATE 2000: 527-531 - [c23]Chauchin Su, Yue-Tsang Chen:
Crosstalk Effect Removal for Analog Measurement in Analog Test Bus. VTS 2000: 403-410
1990 – 1999
- 1999
- [j2]Chauchin Su, Shyh-Jye Jou:
Decentralized BIST Methodology for System Level Interconnects. J. Electron. Test. 15(3): 255-265 (1999) - [c22]Chauchin Su, Yue-Tsang Chen, Chung-Len Lee:
Analog Metrology and Stimulus Selection in a Noisy Environment. Asian Test Symposium 1999: 233-238 - 1998
- [c21]Chauchin Su, Yue-Tsung Chen:
Comprehensive Interconnect BIST Methodology for Virtual Socket Interface. Asian Test Symposium 1998: 259- - [c20]Yue-Tsang Chen, Chauchin Su:
Analog Module Metrology Using MNABST-1 P1149.4 Test Chip. Asian Test Symposium 1998: 378-382 - [c19]Chauchin Su:
A linear optimal test generation algorithm for interconnect testing. ICCAD 1998: 290-295 - [c18]Chauchin Su, Shung-Won Jeng, Yue-Tsang Chen:
Boundary scan BIST methodology for reconfigurable systems. ITC 1998: 774-783 - 1997
- [j1]Shyh-Jye Jou, Chang-Yu Chen, En-Chung Yang, Chau-Chin Su:
A pipelined multiplier-accumulator using a high-speed, low-power static and dynamic full adder design. IEEE J. Solid State Circuits 32(1): 114-118 (1997) - [c17]Chauchin Su, E. Y. Chen, Shyh-Jye Jou:
Structural approach for performance driven ECC circuit synthesis. ASP-DAC 1997: 89-94 - [c16]Chauchin Su, Yi-Ren Cheng, Yue-Tsang Chen, Shing Tenchen:
Analog signal metrology for mixed signal ICs. Asian Test Symposium 1997: 194- - [c15]Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou:
Parasitic Effect Removal for Analog Measurement in P1149.4 Environment. ITC 1997: 499-508 - 1996
- [c14]Chauchin Su, Shyh-Shen Hwang, Shyh-Jye Jou, Yuan-Tzu Ting:
Syndrome Simulation And Syndrome Test For Unscanned Interconnects. Asian Test Symposium 1996: 62-67 - [c13]Chauchin Su, Shyh-Jye Jou, Yuan-Tzu Ting:
Decentralized BIST for 1149.1 and 1149.5 Based Interconnects. ED&TC 1996: 120-125 - [c12]Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou, Yuan-Tzu Ting:
Metrology for analog module testing using analog testability bus. ICCAD 1996: 594-599 - 1995
- [c11]Chauchin Su, Shenshung Chiang, Shyh-Jye Jou:
Impulse response fault model and fault extraction for functional level analog circuit diagnosis. ICCAD 1995: 631-636 - [c10]Wen-Hsing Hsieh, Shyh-Jye Jou, Chauchin Su:
A Parallel Event-Driven MOS Timing Simulator on Distributed-Memory Multiprocessors. ISCAS 1995: 574-577 - [c9]Shyh-Jye Jou, Kou-Fong Liu, Chauchin Su:
Circuits Design Optimization Using Symbolic Approach. ISCAS 1995: 1396-1399 - 1994
- [c8]Chauchin Su:
Random Testing of Interconnects in A Boundary Scan Environment. EDAC-ETC-EUROASIC 1994: 226-231 - [c7]Shyh-Jye Jou, Mei-Fang Perng, Chauchin Su, C. K. Wang:
Hierarchical Techniques for Symbolic Analysis of Large Electronic Circuits. ISCAS 1994: 21-24 - [c6]Chauchin Su, Kychin Hwang, Shyh-Jye Jou:
An IDDQ Based Built-in Concurrent Test Technique for Interconnects in a Boundary-Scan Environment. ITC 1994: 670-676 - 1993
- [c5]Chiyuan Chang, Chauchin Su:
A Universal BIST Methodology for Interconnects. ISCAS 1993: 1615-1618 - [c4]Chauchin Su, Jyrghong Wang:
ECCSyn: a Synthesis Tool for ECC Circuits. ISCAS 1993: 1706-1709 - [c3]Chauchin Su, Kychin Hwang:
A Serial-Scan Test-Vector-Compression Methodology. ITC 1993: 981-988 - 1990
- [c2]Chau-Chin Su, Charles R. Kime:
Multiple path sensitization for hierarchical circuit testing. ITC 1990: 152-161 - [c1]Chau-Chin Su, Charles R. Kime:
Computer-aided design of pseudoexhaustive BIST for semiregular circuits. ITC 1990: 680-689
Coauthor Index
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