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Roope Kaivola
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Publications
- 2022
- [c20]Aarti Gupta, Roope Kaivola, Mihir Parang Mehta, Vaibhav Singh:
Error Correction Code Algorithm and Implementation Verification Using Symbolic Representations. FMCAD 2022: 151-159 - 2013
- [c18]John W. O'Leary, Roope Kaivola, Tom Melham:
Relational STE and theorem proving for formal verification of industrial circuit designs. FMCAD 2013: 97-104 - 2009
- [c16]Roope Kaivola, Rajnish Ghughal, Naren Narasimhan, Amber Telfer, Jesse Whittemore, Sudhindra Pandav, Anna Slobodová, Christopher Taylor, Vladimir A. Frolov, Erik Reeber, Armaghan Naik:
Replacing Testing with Formal Verification in Intel CoreTM i7 Processor Execution Engine Validation. CAV 2009: 414-429 - 2005
- [c14]Roope Kaivola, Armaghan Naik:
Formal verification of high-level conformance with symbolic simulation. HLDVT 2005: 153-159 - 2003
- [j3]Roope Kaivola, Katherine R. Kohatsu:
Proof engineering in the large: formal verification of Pentium?4 floating-point divider. Int. J. Softw. Tools Technol. Transf. 4(3): 323-334 (2003) - 2002
- [c13]Roope Kaivola, Naren Narasimhan:
Formal Verification of the Pentium ® 4 Floating-Point Multiplier. DATE 2002: 20-27 - 2001
- [c12]Roope Kaivola, Katherine R. Kohatsu:
Proof Engineering in the Large: Formal Verification of Pentium® 4 Floating-Point Divider. CHARME 2001: 196-211 - [c11]Roope Kaivola, Naren Narasimhan:
Formal verification of the Pentium(R) 4 multiplier. HLDVT 2001: 115-120 - 2000
- [c10]Mark D. Aagaard, Robert B. Jones, Roope Kaivola, Katherine R. Kohatsu, Carl-Johan H. Seger:
Formal verification of iterative algorithms in microprocessors. DAC 2000: 201-206 - [c9]Roope Kaivola, Mark D. Aagaard:
Divider Circuit Verification with Model Checking and Theorem Proving. TPHOLs 2000: 338-355
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last updated on 2023-09-27 22:51 CEST by the dblp team
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