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Marios C. Papaefthymiou
Publications
- 2007
- [c49]Zhengtao Yu, Marios C. Papaefthymiou, Xun Liu:
Skew spreading for peak current reduction. ACM Great Lakes Symposium on VLSI 2007: 461-464 - [i1]Xun Liu, Yuantao Peng, Marios C. Papaefthymiou:
RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power. CoRR abs/0710.4690 (2007) - 2006
- [j19]Xun Liu, Yuantao Peng, Marios C. Papaefthymiou:
Practical repeater insertion for low power: what repeater library do we need? IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(5): 917-924 (2006) - [c47]Jiyoun Kim, Marios C. Papaefthymiou, José Luis Neves:
Parallelizing post-placement timing optimization. IPDPS 2006 - 2005
- [j17]Xun Liu, Marios C. Papaefthymiou:
HyPE: hybrid power estimation for IP-based systems-on-chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(7): 1089-1103 (2005) - [c45]Xun Liu, Yuantao Peng, Marios C. Papaefthymiou:
RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power. DATE 2005: 1330-1335 - [c41]Jiyoun Kim, José Neves, Marios C. Papaefthymiou:
Multi-Session Partitioning for Parallel Timing Optimization. PDCAT 2005: 598-602 - 2004
- [j16]Xun Liu, Marios C. Papaefthymiou:
A Markov chain sequence generator for power macromodeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(7): 1048-1062 (2004) - [c40]Xun Liu, Yuantao Peng, Marios C. Papaefthymiou:
Practical repeater insertion for low power: what repeater library do we need? DAC 2004: 30-35 - [c39]Jiyoun Kim, Marios C. Papaefthymiou, Athar B. Tayyab:
An Algorithm for Geometric Load Balancing with Two Constraints. IPDPS 2004 - [c34]Dimitrios Velenis, Marios C. Papaefthymiou, Eby G. Friedman:
Clock tree layout design for reduced delay uncertainty. SoCC 2004: 179-180 - 2003
- [j13]Xun Liu, Marios C. Papaefthymiou:
Design of a 20-mb/s 256-state Viterbi decoder. IEEE Trans. Very Large Scale Integr. Syst. 11(6): 965-975 (2003) - [c33]Xun Liu, Marios C. Papaefthymiou:
HyPE: hybrid power estimation for IP-based programmable systems. ASP-DAC 2003: 606-609 - [c32]Dimitrios Velenis, Marios C. Papaefthymiou, Eby G. Friedman:
Reduced Delay Uncertainty in High Performance Clock Distribution Networks. DATE 2003: 10068-10075 - 2002
- [j11]Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman:
Retiming and clock scheduling for digital circuit optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(2): 184-203 (2002) - [c29]Xun Liu, Marios C. Papaefthymiou:
Design of a high-throughput low-power IS95 Viterbi decoder. DAC 2002: 263-268 - [c28]Xun Liu, Marios C. Papaefthymiou:
A Markov chain sequence generator for power macromodeling. ICCAD 2002: 404-411 - [c27]Xun Liu, Marios C. Papaefthymiou:
Incorporation of input glitches into power macromodeling. ISCAS (4) 2002: 846-849 - 2001
- [c23]Xun Liu, Marios C. Papaefthymiou:
A static power estimation methodolodgy for IP-based design. DATE 2001: 280-289 - [c22]Dimitrios Velenis, Eby G. Friedman, Marios C. Papaefthymiou:
A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty. ISCAS (4) 2001: 422-425 - 1999
- [c18]Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman:
Maximizing Performance by Retiming and Clock Skew Scheduling. DAC 1999: 231-236 - [c17]Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman:
Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits. DATE 1999: 643-649
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