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Dinesh Bhatia
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Publications
- 2006
- [j12]PariVallal Kannan, Dinesh Bhatia:
Interconnect estimation for FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(8): 1523-1534 (2006) - 2005
- [j10]Shankar Balachandran, Dinesh Bhatia:
A priori wirelength and interconnect estimation based on circuit characteristic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(7): 1054-1065 (2005) - [c41]Shankar Balachandran, Dinesh Bhatia:
Timing Aware Interconnect Prediction Models for FPGAs. FPL 2005: 167-172 - 2004
- [j9]PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia:
On metrics for comparing interconnect estimation methods for FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 12(4): 381-385 (2004) - [c38]PariVallal Kannan, Dinesh Bhatia:
Estimating Pre-Placement FPGA Interconnection Requirements. VLSI Design 2004: 869- - 2003
- [c36]PariVallal Kannan, Dinesh Bhatia:
Interconnect Estimation for FPGAs under Timing Driven Domains. ICCD 2003: 344-349 - [c35]Shankar Balachandran, Dinesh Bhatia:
A-priori wirelength and interconnect estimation based on circuit characteristics. SLIP 2003: 77-84 - 2002
- [c34]PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia:
On metrics for comparing routability estimation methods for FPGAs. DAC 2002: 70-75 - [c33]PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia:
Rapid and Reliable Routability Estimation for FPGAs. FPL 2002: 242-252 - [c32]Shankar Balachandran, PariVallal Kannan, Dinesh Bhatia:
On Routing Demand and Congestion Estimation for FPGAs. ASP-DAC/VLSI Design 2002: 639-646 - 2001
- [c31]PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia:
fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits. FPL 2001: 37-47 - [c30]PariVallal Kannan, Dinesh Bhatia:
Tightly Integrated Placement and Routing for FPGAs. FPL 2001: 233-242 - 1999
- [j5]Karthikeya M. Gajjala Purna, Dinesh Bhatia:
Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers. IEEE Trans. Computers 48(6): 579-590 (1999) - [c27]Dinesh Bhatia, Kuldeep S. Simha, PariVallal Kannan:
NEBULA: A Partially and Dynamically Reconfigurable Architecture. FPL 1999: 405-410 - 1998
- [c24]Karthikeya M. Gajjala Purna, Dinesh Bhatia:
Temporal Partitioning and Scheduling for Reconfigurable Computing. FCCM 1998: 329-330 - [c22]Dinesh Bhatia, PariVallal Kannan, Kuldeep S. Simha, Karthikeya M. Gajjala Purna:
REACT: Reactive Environment for Runtime Reconfiguration. FPL 1998: 209-217 - [c20]Karthikeya M. Gajjala Purna, Dinesh Bhatia:
Partitioning in time: a paradigm for reconfigurable computing. ICCD 1998: 340-345 - [c19]Karthikeya M. Gajjala Purna, Dinesh Bhatia:
Emulating Large Designs on Small Reconfigurable Hardware. International Workshop on Rapid System Prototyping 1998: 58-63
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last updated on 2023-12-14 21:27 CET by the dblp team
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