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Daniel Sánchez 0004

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Juan L. Aragón

> Home > Persons > Daniel Sánchez 0004

Publications

2015
[j5]
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  - journals/dc/SanchezCGA15
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  - https://dblp.org/rec/journals/dc/SanchezCGA15
Daniel Sánchez, Juan M. Cebrian, José M. García, Juan L. Aragón:
Soft-error mitigation by means of decoupled transactional memory threads. Distributed Comput. 28(2): 75-90 (2015)
2014
[j4]
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  - journals/tjs/CebrianSAK14
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Juan M. Cebrian, Daniel Sánchez, Juan L. Aragón, Stefanos Kaxiras:
Managing power constraints in a single-core scenario through power tokens. J. Supercomput. 68(1): 414-442 (2014)
2013
[j3]
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  - journals/computing/CebrianSAK13
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Juan M. Cebrian, Daniel Sánchez, Juan L. Aragón, Stefanos Kaxiras:
Efficient inter-core power and thermal balancing for multicore processors. Computing 95(7): 537-566 (2013)
[j2]
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  - journals/taco/SanchezSCGA13
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Daniel Sánchez, Yiannakis Sazeides, Juan M. Cebrian, José M. García, Juan L. Aragón:
Modeling the impact of permanent faults in caches. ACM Trans. Archit. Code Optim. 10(4): 29:1-29:23 (2013)
2012
[j1]
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  - journals/tjs/SanchezAG12
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Daniel Sánchez, Juan L. Aragón, José M. García:
A fault-tolerant architecture for parallel applications in tiled-CMPs. J. Supercomput. 61(3): 997-1023 (2012)
2011
[c4]
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  dblp key:
  - conf/iolts/SanchezSAG11
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Daniel Sánchez, Yiannakis Sazeides, Juan L. Aragón, José M. García:
An analytical model for the calculation of the Expected Miss Ratio in faulty caches. IOLTS 2011: 252-257
2010
[c3]
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  - conf/hipc/SanchezAG10
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Daniel Sánchez, Juan L. Aragón, José M. García:
A log-based redundant architecture for reliable parallel computation. HiPC 2010: 1-10
2009
[c2]
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  - conf/europar/SanchezAG09
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Daniel Sánchez, Juan L. Aragón, José M. García:
REPAS: Reliable Execution for Parallel ApplicationS in Tiled-CMPs. Euro-Par 2009: 321-333
[c1]
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Daniel Sánchez, Juan L. Aragón, José M. García:
Extending SRT for parallel applications in tiled-CMP architectures. IPDPS 2009: 1-8

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