Eric Chang

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Howard Mao

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Publications

2019
[j6]
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Steven Bailey, Paul Rigge, Jaeduk Han, Richard Lin, Eric Chang, Howard Mao, Zhongkai Wang, Chick Markley, Adam M. Izraelevitz, Angie Wang, Nathan Narevsky, Woo-Rham Bae, Steve Shauck, Sergio Montano, Justin Norsworthy, Munir Razzaque, Wen Hau Ma, Akalu Lentiro, Matthew Doerflein, Darin Heckendorn, Jim McGrath, Franco DeSeta, Ronen Shoham, Mike Stellfox, Mark Snowden, Joseph Cole, Dan Fuhrman, Brian C. Richards, Jonathan Bachrach, Elad Alon, Borivoje Nikolic:
A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance. IEEE J. Solid State Circuits 54(10): 2786-2801 (2019)
2018
[c53]
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Stevo Bailey, Jaeduk Han, Paul Rigge, Richard Lin, Eric Chang, Howard Mao, Zhongkai Wang, Chick Markley, Adam M. Izraelevitz, Angie Wang, Nathan Narevsky, Woo-Rham Bae, Steve Shauck, Sergio Montano, Justin Norsworthy, Munir Razzaque, Wen Hau Ma, Akalu Lentiro, Matthew Doerflein, Darin Heckendorn, Jim McGrath, Franco DeSeta, Ronen Shoham, Mike Stellfox, Mark Snowden, Joseph Cole, Dan Fuhrman, Brian C. Richards, Jonathan Bachrach, Elad Alon, Borivoje Nikolic:
A Generated Multirate Signal Analysis RISC-V SoC in 16nm FinFET. A-SSCC 2018: 285-288
2017
[c50]
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Angie Wang, Brian C. Richards, Daniel Palmer Dabbelt, Howard Mao, Stevo Bailey, Jaeduk Han, Eric Chang, James Dunn, Elad Alon, Borivoje Nikolic:
A 0.37mm² LTE/Wi-Fi compatible, memory-based, runtime-reconfigurable 2ⁿ3^m5^k FFT accelerator integrated with a RISC-V core in 16nm FinFET. A-SSCC 2017: 305-308

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