Zhengya Zhang

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Youn Sung Park

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Publications

2015
[j13]
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Youn Sung Park, Yaoyu Tao, Zhengya Zhang:
A Fully Parallel Nonbinary LDPC Decoder With Fine-Grained Dynamic Clock Gating. IEEE J. Solid State Circuits 50(2): 464-475 (2015)
2014
[j10]
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  - journals/jssc/ParkBSZ14
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Youn Sung Park, David T. Blaauw, Dennis Sylvester, Zhengya Zhang:
Low-Power High-Throughput LDPC Decoder Using Non-Refresh Embedded DRAM. IEEE J. Solid State Circuits 49(3): 783-794 (2014)
[c20]
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  - conf/vlsic/ParkTSZ14
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Youn Sung Park, Yaoyu Tao, Shuanghong Sun, Zhengya Zhang:
A 4.68Gb/s belief propagation polar decoder with bit-splitting register file. VLSIC 2014: 1-2
2013
[c14]
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  - conf/isscc/ParkTZ13
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Youn Sung Park, Yaoyu Tao, Zhengya Zhang:
A 1.15Gb/s fully parallel nonbinary LDPC decoder with fine-grained dynamic clock gating. ISSCC 2013: 422-423
2012
[c13]
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  - conf/fpga/LiPZ12
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Haoran Li, Youn Sung Park, Zhengya Zhang:
Reconfigurable architecture and automated design flow for rapid FPGA-based LDPC code emulation. FPGA 2012: 167-170
[c12]
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  - conf/iscas/TaoPZ12
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Yaoyu Tao, Youn Sung Park, Zhengya Zhang:
High-throughput architecture and implementation of regular (2, dc) nonbinary LDPC decoders. ISCAS 2012: 2625-2628
[c11]
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Youn Sung Park, David T. Blaauw, Dennis Sylvester, Zhengya Zhang:
A 1.6-mm² 38-mW 1.5-Gb/s LDPC decoder enabled by refresh-free embedded DRAM. VLSIC 2012: 114-115

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