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Nithin George

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Paolo Ienne

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Publications

2017
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  - journals/access/AsiaticiGVFI17
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  - https://dblp.org/rec/journals/access/AsiaticiGVFI17
Mikhail Asiatici, Nithin George, Kizheppatt Vipin, Suhaib A. Fahmy, Paolo Ienne:
Virtualized Execution Runtime for FPGA Accelerators in the Cloud. IEEE Access 5: 1900-1910 (2017)
[j1]
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  - journals/access/AndradeGKNPSIF017
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  - https://dblp.org/rec/journals/access/AndradeGKNPSIF017
João Andrade, Nithin George, Kimon Karras, David Novo, Frederico Pratas, Leonel Sousa, Paolo Ienne, Gabriel Falcão, Vítor Silva:
Design Space Exploration of LDPC Decoders Using High-Level Synthesis. IEEE Access 5: 14600-14615 (2017)
2016
[c8]
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  - conf/fpl/AsiaticiGVFI16
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Mikhail Asiatici, Nithin George, Kizheppatt Vipin, Suhaib A. Fahmy, Paolo Ienne:
Designing a virtual runtime for FPGA accelerators in the cloud. FPL 2016: 1-2
[c7]
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  dblp key:
  - conf/fpt/JosipovicGI16
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  - https://dblp.org/rec/conf/fpt/JosipovicGI16
Lana Josipovic, Nithin George, Paolo Ienne:
Enriching C-based High-Level Synthesis with parallel pattern templates. FPT 2016: 177-180
2015
[c6]
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  - conf/fccm/AndradeGKNSIF15
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João Andrade, Nithin George, Kimon Karras, David Novo, Vítor Manuel Mendes da Silva, Paolo Ienne, Gabriel Falcão Paiva Fernandes:
Fast Design Space Exploration Using Vivado HLS: Non-binary LDPC Decoders. FCCM 2015: 97
[c5]
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  - conf/fpl/AndradeGKNSIF15
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João Andrade, Nithin George, Kimon Karras, David Novo, Vítor Manuel Mendes da Silva, Paolo Ienne, Gabriel Falcão Paiva Fernandes:
From low-architectural expertise up to high-throughput non-binary LDPC decoders: Optimization guidelines using high-level synthesis. FPL 2015: 1-8
[c4]
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  - conf/fpl/GeorgeLNOAOI15
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Nithin George, HyoukJoong Lee, David Novo, Muhsen Owaida, David Andrews, Kunle Olukotun, Paolo Ienne:
Automatic support for multi-module parallelism from computational patterns. FPL 2015: 1-8
2014
[c3]
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  - conf/fpl/GeorgeLNRBSOOI14
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Nithin George, HyoukJoong Lee, David Novo, Tiark Rompf, Kevin J. Brown, Arvind K. Sujeeth, Martin Odersky, Kunle Olukotun, Paolo Ienne:
Hardware system synthesis from Domain-Specific Languages. FPL 2014: 1-8
2013
[c2]
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  - conf/fpt/GeorgeNROI13
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Nithin George, David Novo, Tiark Rompf, Martin Odersky, Paolo Ienne:
Making domain-specific hardware synthesis tools cost-efficient. FPT 2013: 120-127
2012
[c1]
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  dblp key:
  - conf/fpga/MoctarGPILB12
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Yehdhih Ould Mohammed Moctar, Nithin George, Hadi Parandeh-Afshar, Paolo Ienne, Guy G. F. Lemieux, Philip Brisk:
Reducing the cost of floating-point mantissa alignment and normalization in FPGAs. FPGA 2012: 255-264

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