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Deog-Kyoon Jeong

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Hong-Seok Choi

> Home > Persons > Deog-Kyoon Jeong

Publications

2021
[c76]
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  dblp key:
  - conf/isocc/ChoiRLPLHJ21
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  persistent URL:
  - https://dblp.org/rec/conf/isocc/ChoiRLPLHJ21
Hong-Seok Choi, Seungha Roh, Sanghee Lee, Jung-Hoon Park, Kwanghoon Lee, Young-Ha Hwang, Deog-Kyoon Jeong:
A 6b 48-GS/s Asynchronous 2b/cycle Time-Interleaved ADC in 28-nm CMOS. ISOCC 2021: 127-128
2020
[j91]
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  - journals/tcas/DoHCJ20
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Hyungrok Do, Jeongho Hwang, Hong-Seok Choi, Deog-Kyoon Jeong:
A 48 Gb/s PAM-4 Transmitter With 3-Tap FFE Based on Double-Shielded Coplanar Waveguide in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 67-II(9): 1569-1573 (2020)
2019
[c55]
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  - electronic edition @ ieee.org
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  - conf/ofc/HwangDCJKKJ19
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Jeongho Hwang, Hyungrok Do, Hong-Seok Choi, Gyu-Seob Jeong, Daehyun Koh, Sungwoo Kim, Deog-Kyoon Jeong:
56Gb/s PAM-4 VCSEL Transmitter with Quarter-Rate Forwarded Clock using 65nm CMOS Circuits. OFC 2019: 1-3
[c51]
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  - conf/vlsic/HwangCDJKPKJ19
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Jeongho Hwang, Hong-Seok Choi, Hyungrok Do, Gyu-Seob Jeong, Daehyun Koh, Kwanseo Park, Sungwoo Kim, Deog-Kyoon Jeong:
A 64Gb/s 2.29pJ/b PAM-4 VCSEL Transmitter With 3-Tap Asymmetric FFE in 65nm CMOS. VLSI Circuits 2019: 268-
2018
[j72]
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  - journals/tcas/JeongHCDKYLPKLJ18
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  - https://dblp.org/rec/journals/tcas/JeongHCDKYLPKLJ18
Gyu-Seob Jeong, Jeongho Hwang, Hong-Seok Choi, Hyungrok Do, Daehyun Koh, Daeyoung Yun, Jinhyung Lee, Kwanseo Park, Han-Gon Ko, Kwangho Lee, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong:
25-Gb/s Clocked Pluggable Optics for High-Density Data Center Interconnections. IEEE Trans. Circuits Syst. II Express Briefs 65-II(10): 1395-1399 (2018)
[j69]
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  - journals/tcas/ChoiHJKJ18
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Hong-Seok Choi, Jeongho Hwang, Gyu-Seob Jeong, Gyungock Kim, Deog-Kyoon Jeong:
A 35-Gb/s 0.65-pJ/b Asymmetric Push-Pull Inverter-Based VCSEL Driver With Series Inductive Peaking in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 65-II(12): 1824-1828 (2018)
[c46]
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  - conf/islped/HwangCDJKPJ18
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Jeongho Hwang, Hong-Seok Choi, Hyungrok Do, Gyu-Seob Jeong, Daehyun Koh, Seong Ho Park, Deog-Kyoon Jeong:
4-Channel Push-Pull VCSEL Drivers for HDMI Active Optical Cable in 0.18-μm CMOS. ISLPED 2018: 11:1-11:6

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