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Yosinori Watanabe

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Harry Hsieh

> Home > Persons > Yosinori Watanabe

Publications

2009
[j12]
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  dblp key:
  - journals/dafes/CheungCHDSW09
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  - https://dblp.org/rec/journals/dafes/CheungCHDSW09
Eric Cheung, Xi Chen, Harry Hsieh, Abhijit Davare, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe:
Runtime deadlock analysis for system level design. Des. Autom. Embed. Syst. 13(4): 287-310 (2009)
2005
[c34]
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  dblp key:
  - conf/dac/ChenDHSW05
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  - https://dblp.org/rec/conf/dac/ChenDHSW05
Xi Chen, Abhijit Davare, Harry Hsieh, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe:
Simulation based deadlock analysis for system level designs. DAC 2005: 260-265
2004
[j6]
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  - journals/tcad/ChenHBW04
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  - https://dblp.org/rec/journals/tcad/ChenHBW04
Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe:
Logic of constraints: a quantitative performance and functional constraint formalism. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(8): 1243-1255 (2004)
2003
[j5]
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  - journals/computer/BalarinWHLPS03
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  - https://dblp.org/rec/journals/computer/BalarinWHLPS03
Felice Balarin, Yosinori Watanabe, Harry Hsieh, Luciano Lavagno, Claudio Passerone, Alberto L. Sangiovanni-Vincentelli:
Metropolis: An Integrated Electronic System Design Environment. Computer 36(4): 45-52 (2003)
[j4]
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  - journals/dafes/ChenHBW03
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Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe:
Formal Verification for Embedded System Designs. Des. Autom. Embed. Syst. 8(2-3): 139-153 (2003)
[c29]
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  dblp key:
  - conf/acsd/ChenHBW03
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Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe:
Case Studies of Model Checking for Embedded System Designs. ACSD 2003: 20-28
[c27]
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  - conf/dac/ChenHBW03
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Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe:
Automatic trace analysis for logic of constraints. DAC 2003: 460-465
[c23]
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  dblp key:
  - conf/date/ChenHBW03
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Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe:
Automatic Generation of Simulation Monitors from Quantitative Constraint Formula. DATE 2003: 11174-11175
[c22]
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  dblp key:
  - conf/hldvt/ChenHBW03
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Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe:
Verifying LOC based functional and performance constraints. HLDVT 2003: 83-88
[p1]
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  - books/sp/03/0024HBW03
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  - https://dblp.org/rec/books/sp/03/0024HBW03
Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe:
Simulation Trace Verification for Quantitative Constraints. Embedded Software for SoC 2003: 275-285
2002
[c15]
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  dblp key:
  - conf/hldvt/ChenCHBW02
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  - https://dblp.org/rec/conf/hldvt/ChenCHBW02
Xi Chen, Fang Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe:
Formal verification of embedded system designs at multiple levels of abstraction. HLDVT 2002: 125-130

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