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Dong Xiang
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Publications
- 2012
- [j36]Dong Xiang, Zhen Chen, Laung-Terng Wang:
Scan Flip-Flop Grouping to Compress Test Data and Compact Test Responses for Launch-on-Capture Delay Testing. ACM Trans. Design Autom. Electr. Syst. 17(2): 18:1-18:24 (2012) - 2011
- [j33]Zhen Chen, Krishnendu Chakrabarty, Dong Xiang:
MVP: Minimum-Violations Partitioning for Reducing Capture Power in At-Speed Delay-Fault Testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(11): 1762-1767 (2011) - [c53]Dong Xiang, Zhen Chen:
Selective Test Response Collection for Low-Power Scan Testing with Well-Compressed Test Data. Asian Test Symposium 2011: 40-45 - [c52]Zhen Chen, Jia Li, Dong Xiang, Yu Huang:
Virtual Circuit Model for Low Power Scan Testing in Linear Decompressor-Based Compression Environment. Asian Test Symposium 2011: 96-101 - [c51]Zhen Chen, Sharad C. Seth, Dong Xiang, Bhargab B. Bhattacharya:
Diagnosis of Multiple Scan-Chain Faults in the Presence of System Logic Defects. Asian Test Symposium 2011: 297-302 - 2010
- [j31]Zhen Chen, J. Feng, Dong Xiang, Boxue Yin:
Scan chain configuration based X-filling for low power and high quality testing. IET Comput. Digit. Tech. 4(1): 1-13 (2010) - [j30]Zhen Chen, Sharad C. Seth, Dong Xiang, Bhargab B. Bhattacharya:
PVT: Unified Reduction of Test Power, Volume, and Test Time Using Double-Tree Scan Architecture. J. Low Power Electron. 6(3): 457-468 (2010) - [j28]Zhen Chen, Dong Xiang:
A Novel Test Application Scheme for High Transition Fault Coverage and Low Test Cost. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(6): 966-976 (2010) - [c49]Zhen Chen, Krishnendu Chakrabarty, Dong Xiang:
MVP: Capture-power reduction with minimum-violations partitioning for delay testing. ICCAD 2010: 149-154 - [c45]Zhen Chen, Sharad C. Seth, Dong Xiang, Bhargab B. Bhattacharya:
A Unified Solution to Scan Test Volume, Time, and Power Minimization. VLSI Design 2010: 9-14 - [c44]Zhen Chen, Dong Xiang:
Low-capture-power at-speed testing using partial launch-on-capture test scheme. VTS 2010: 141-146 - [c43]Zhen Chen, Sharad C. Seth, Dong Xiang:
A novel hybrid delay testing scheme with low test power, volume, and time. VTS 2010: 307-312 - 2009
- [c42]Zhen Chen, Boxue Yin, Dong Xiang:
Conflict driven scan chain configuration for high transition fault coverage and low test power. ASP-DAC 2009: 666-671 - [c40]Zhen Chen, Dong Xiang, Boxue Yin:
A power-effective scan architecture using scan flip-flops clustering and post-generation filling. ACM Great Lakes Symposium on VLSI 2009: 517-522 - [c37]Boxue Yin, Dong Xiang, Zhen Chen:
New Techniques for Accelerating Small Delay ATPG and Generating Compact Test Sets. VLSI Design 2009: 221-226 - [c36]Zhen Chen, Dong Xiang, Boxue Yin:
The ATPG Conflict-Driven Scheme for High Transition Fault Coverage and Low Test Cost. VTS 2009: 146-151 - 2008
- [c33]Dong Xiang, Yi Pan, Qi Wang, Zhen Chen:
Deadlock-Free Fully Adaptive Routing in 2-Dimensional Tori Based on New Virtual Network Partitioning Scheme. ICDCS 2008: 454-461
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