Chih-Yen Lo

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Jin-Fu Li 0001

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Publications

2020
[c15]
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Tsung-Fu Hsieh, Jin-Fu Li, Jenn-Shiang Lai, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou:
Refresh Power Reduction of DRAMs in DNN Systems Using Hybrid Voting and ECC Method. ITC-Asia 2020: 41-46
2018
[c14]
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  - conf/aspdac/WuLLLKC18
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Kuan-Te Wu, Jin-Fu Li, Chih-Yen Lo, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou:
A channel-sharable built-in self-test scheme for multi-channel DRAMs. ASP-DAC 2018: 245-250
2017
[c12]
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Tsung-Fu Hsieh, Jin-Fu Li, Kuan-Te Wu, Jenn-Shiang Lai, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou:
Software-hardware-cooperated built-in self-test scheme for channel-based DRAMs. ITC-Asia 2017: 107-111
2016
[c11]
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  - conf/ats/LinCLLKC16
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Tzu-Ying Lin, Yong-Xiao Chen, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou:
A Test Method for Finding Boundary Currents of 1T1R Memristor Memories. ATS 2016: 281-286
[c10]
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  - conf/itc/HouCLLKC16
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Chih-Sheng Hou, Yong-Xiao Chen, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou:
A built-in self-repair scheme for DRAMs with spare rows, columns, and bits. ITC 2016: 1-7
2015
[j3]
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  - journals/dt/ChouLYLKC15
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Che-Wei Chou, Jin-Fu Li, Yun-Chao Yu, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou:
Hierarchical Test Integration Methodology for 3-D ICs. IEEE Des. Test 32(4): 59-70 (2015)
[c9]
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  - conf/vlsi-dat/YangLYWLCLKC15
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Chi-Chun Yang, Jin-Fu Li, Yun-Chao Yu, Kuan-Te Wu, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou:
A hybrid built-in self-test scheme for DRAMs. VLSI-DAT 2015: 1-4
2014
[c8]
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  - conf/ats/YouYLLCLKCW14
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Yun-Chao You, Chi-Chun Yang, Jin-Fu Li, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
BIST-Assisted Tuning Scheme for Minimizing IO-Channel Power of TSV-Based 3D DRAMs. ATS 2014: 1-6
[c7]
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  - conf/ats/WuLYHYKCL14
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Kuan-Te Wu, Jin-Fu Li, Yun-Chao Yu, Chih-Sheng Hou, Chi-Chun Yang, Ding-Ming Kwai, Yung-Fa Chou, Chih-Yen Lo:
Intra-channel Reconfigurable Interface for TSV and Micro Bump Fault Tolerance in 3-D RAMs. ATS 2014: 143-148
2013
[c6]
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  - conf/vlsi-dat/HouLLKCW13
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Chih-Sheng Hou, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
An FPGA-based test platform for analyzing data retention time distribution of DRAMs. VLSI-DAT 2013: 1-4
[c5]
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  - conf/vts/YouHCLLKCW13
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Yun-Chao You, Chih-Sheng Hou, Li-Jung Chang, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
A hybrid ECC and redundancy technique for reducing refresh power of DRAMs. VTS 2013: 1-6
2012
[c4]
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  - conf/itc/YouCLLKCW12
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Yun-Chao You, Che-Wei Chou, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
A built-in self-test scheme for 3D RAMs. ITC 2012: 1-9

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