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Hideki Ando
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Publications
- 2022
- [j13]Yasutaka Matsuda, Ryota Shioya, Hideki Ando:
Reducing Energy Consumption of Wakeup Logic through Double-Stage Tag Comparison. IEICE Trans. Inf. Syst. 105-D(2): 320-332 (2022) - 2019
- [j12]Reoma Matsuo, Ryota Shioya, Hideki Ando:
Improving the Instruction Fetch Throughput with Dynamically Configuring the Fetch Pipeline. IEEE Comput. Archit. Lett. 18(2): 170-173 (2019) - 2018
- [j11]Keita Doi, Ryota Shioya, Hideki Ando:
Performance Improvement Techniques in Tightly Coupled Multicore Architectures for Single-Thread Applications. J. Inf. Process. 26: 445-460 (2018) - [c15]Yasumasa Chidai, Kojiro Izuoka, Ryota Shioya, Masahiro Goshima, Hideki Ando:
A Tightly Coupled Heterogeneous Core with Highly Efficient Low-Power Mode. ARCS 2018: 211-224 - [c14]Shinji Sakai, Taishi Suenaga, Ryota Shioya, Hideki Ando:
Rearranging Random Issue Queue with High IPC and Short Delay. ICCD 2018: 123-131 - 2016
- [j10]Hideki Ando, Ryota Shioya:
Performance of Dynamic Instruction Window Resizing for a Given Power Budget under DVFS Control. IEICE Trans. Inf. Syst. 99-D(2): 341-350 (2016) - [j9]Ryota Shioya, Hideki Ando:
Improvement of Renamed Trace Cache through the Reduction of Dependent Path Length for High Energy Efficiency. IEICE Trans. Inf. Syst. 99-D(3): 630-640 (2016) - [j8]Ryota Shioya, Ryo Takami, Masahiro Goshima, Hideki Ando:
FXA: Executing Instructions in Front-End for Energy Efficiency. IEICE Trans. Inf. Syst. 99-D(4): 1092-1107 (2016) - 2014
- [c12]Ryota Shioya, Hideki Ando:
Energy efficiency improvement of renamed trace cache through the reduction of dependent path length. ICCD 2014: 416-423 - [c11]Ryota Shioya, Masahiro Goshima, Hideki Ando:
A Front-End Execution Architecture for High Energy Efficiency. MICRO 2014: 419-431
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