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Mau-Chung Frank Chang

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Zuow-Zun Chen

> Home > Persons > Mau-Chung Frank Chang

Publications

2017
[j50]
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  - journals/jssc/ChenKLHWC17
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  persistent URL:
  - https://dblp.org/rec/journals/jssc/ChenKLHWC17
Zuow-Zun Chen, Yen-Cheng Kuan, Yilei Li, Boyu Hu, Chien-Heng Wong, Mau-Chung Frank Chang:
DPLL for Phase Noise Cancellation in Ring Oscillator-Based Quadrature Receivers. IEEE J. Solid State Circuits 52(4): 1134-1143 (2017)
2016
[j46]
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  - journals/jssc/ZhaoCDLHVXKTRC16
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  - https://dblp.org/rec/journals/jssc/ZhaoCDLHVXKTRC16
Yan Zhao, Zuow-Zun Chen, Yuan Du, Yilei Li, Richard Al Hadi, Gabriel Virbila, Yinuo Xu, Yanghyo Kim, Adrian Tang, Theodore Reck, Mau-Chung Frank Chang:
A 0.56 THz Phase-Locked Frequency Synthesizer in 65 nm CMOS Technology. IEEE J. Solid State Circuits 51(12): 3005-3019 (2016)
[j45]
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  dblp key:
  - journals/tcas/HuRCJC16
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  - https://dblp.org/rec/journals/tcas/HuRCJC16
Boyu Hu, Fengbo Ren, Zuow-Zun Chen, Xicheng Jiang, Mau-Chung Frank Chang:
An 8-Bit Compressive Sensing ADC With 4-GS/s Equivalent Speed Utilizing Self-Timed Pipeline SAR-Binary-Search. IEEE Trans. Circuits Syst. II Express Briefs 63-II(10): 934-938 (2016)
[c50]
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  dblp key:
  - conf/isscc/ZhaoCVXHK0RCJHC16
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  - https://dblp.org/rec/conf/isscc/ZhaoCVXHK0RCJHC16
Yan Zhao, Zuow-Zun Chen, Gabriel Virbila, Yinuo Xu, Richard Al Hadi, Yanghyo Kim, Adrian Tang, Theodore Reck, Huan-Neng Ron Chen, Chewnpu Jou, Fu-Lung Hsueh, Mau-Chung Frank Chang:
2.1 An integrated 0.56THz frequency synthesizer with 21GHz locking range and -74dBc/Hz phase noise at 1MHz offset in 65nm CMOS. ISSCC 2016: 36-37
[c47]
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  dblp key:
  - conf/vlsic/ChenLKHWC16
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  - https://dblp.org/rec/conf/vlsic/ChenLKHWC16
Zuow-Zun Chen, Yilei Li, Yen-Cheng Kuan, Boyu Hu, Chien-Heng Wong, Mau-Chung Frank Chang:
Digital PLL for phase noise cancellation in ring oscillator-based I/Q receivers. VLSI Circuits 2016: 1-2
[c46]
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  - conf/vlsic/DuCLWDHKCLC16
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  - https://dblp.org/rec/conf/vlsic/DuCLWDHKCLC16
Yuan Du, Wei-Han Cho, Yilei Li, Chien-Heng Wong, Jieqiong Du, Po-Tsang Huang, Yanghyo Kim, Zuow-Zun Chen, Sheau Jiung Lee, Mau-Chung Frank Chang:
A 16Gb/s 14.7mW tri-band cognitive serial link transmitter with forwarded clock to enable PAM-16 / 256-QAM and channel response detection in 28 nm CMOS. VLSI Circuits 2016: 1-2
2015
[c43]
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  - conf/isscc/ChenWSZMKCJTHC15
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Zuow-Zun Chen, Yen-Hsiang Wang, Jaewook Shin, Yan Zhao, Seyed Arash Mirhaj, Yen-Cheng Kuan, Huan-Neng Ron Chen, Chewnpu Jou, Ming-Hsien Tsai, Fu-Lung Hsueh, Mau-Chung Frank Chang:
14.9 Sub-sampling all-digital fractional-N frequency synthesizer with -111dBc/Hz in-band phase noise and an FOM of -242dB. ISSCC 2015: 1-3
[c42]
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  dblp key:
  - conf/isscc/DuZH0ZLCHC15
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  - https://dblp.org/rec/conf/isscc/DuZH0ZLCHC15
Li Du, Yan Zhang, Frank Hsiao, Adrian Tang, Yan Zhao, Yilei Li, Zuow-Zun Chen, Liting Huang, Mau-Chung Frank Chang:
6.7 A 2.3mW 11cm-range bootstrapped and correlated-double-sampling (BCDS) 3D touch sensor for mobile devices. ISSCC 2015: 1-3

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