Laurent Fesquet

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Abdelkarim Cherkaoui

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Publications

2021
[j14]
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Jérémy Belot, Abdelkarim Cherkaoui, Raphaël Laurent, Laurent Fesquet:
An Area- and Power-Efficient Stochastic Number Generator for Bayesian Sensor Fusion Circuits. IEEE Des. Test 38(6): 69-77 (2021)
[c111]
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  - conf/icecsys/BelotCLF21
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Jérémy Belot, Abdelkarim Cherkaoui, Raphaël Laurent, Laurent Fesquet:
An Energy Efficient Multi-Rail Architecture for Stochastic Computing: A Bayesian Sensor Fusion Case Study. ICECS 2021: 1-5
2020
[c109]
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  - conf/async/GimenezCF20
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Grégoire Gimenez, Abdelkarim Cherkaoui, Laurent Fesquet:
A Self-Timed Ring based PUF. ASYNC 2020: 69-77
2018
[c91]
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  - conf/async/GimenezCCF18
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Gregoire Gimenez, Abdelkarim Cherkaoui, Guillaume Cogniard, Laurent Fesquet:
Static Timing Analysis of Asynchronous Bundled-Data Circuits. ASYNC 2018: 110-118
[c90]
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  - conf/coolchips/CoustansCFTSEK18
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Mathieu Coustans, Abdelkarim Cherkaoui, Laurent Fesquet, Christian Terrier, Stephanie Salgado, Thomas Eberhardt, Maher Kayal:
Subthreshold logic for low-area and energy efficient true random number generator. COOL CHIPS 2018: 1-3
[c88]
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  - conf/dcis/ElissatiECRF18
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Oussama Elissati, Assia El-Hadbi, Abdelkarim Cherkaoui, Sébastien Rieubon, Laurent Fesquet:
Low Phase-Noise CMOS Quadrature Oscillator based on (N × 4)-stage Self-Timed Ring. DCIS 2018: 1-5
2017
[c84]
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  - conf/async/SimaticCBBF17
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Jean Simatic, Abdelkarim Cherkaoui, François Bertrand, Rodrigo Possamai Bastos, Laurent Fesquet:
A Practical Framework for Specification, Verification, and Design of Self-Timed Pipelines. ASYNC 2017: 65-72
[c78]
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  - conf/icecsys/BertrandCSMF17
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François Bertrand, Abdelkarim Cherkaoui, Jean Simatic, Anthony Maure, Laurent Fesquet:
CAR: On the highway towards de-synchronization. ICECS 2017: 339-343
[c74]
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  - conf/ivsw/GimenezCFF17
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Gregoire Gimenez, Abdelkarim Cherkaoui, Raphael Frisch, Laurent Fesquet:
Self-timed Ring based True Random Number Generator: Threat model and countermeasures. IVSW 2017: 31-38
[c72]
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  - conf/newcas/El-HadbiCESF17
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Assia El-Hadbi, Abdelkarim Cherkaoui, Oussama Elissati, Jean Simatic, Laurent Fesquet:
On-the-fly and sub-gate-delay resolution TDC based on self-timed ring: A proof of concept. NEWCAS 2017: 305-308
2016
[c63]
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  - conf/sbcci/SimaticCBF16
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Jean Simatic, Abdelkarim Cherkaoui, Rodrigo Possamai Bastos, Laurent Fesquet:
New asynchronous protocols for enhancing area and throughput in bundled-data pipelines. SBCCI 2016: 1-6
2014
[c51]
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  - conf/newcas/FesquetCE14
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Laurent Fesquet, Abdelkarim Cherkaoui, Oussama Elissati:
Self-timed rings as low-phase noise programmable oscillators. NEWCAS 2014: 409-412
2013
[c47]
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  - conf/async/CherkaouiFAF13
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Abdelkarim Cherkaoui, Viktor Fischer, Alain Aubert, Laurent Fesquet:
A Self-Timed Ring Based True Random Number Generator. ASYNC 2013: 99-106
[c46]
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  - conf/ches/CherkaouiFFA13
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Abdelkarim Cherkaoui, Viktor Fischer, Laurent Fesquet, Alain Aubert:
A Very High Speed True Random Number Generator with Entropy Assessment. CHES 2013: 179-196
2012
[c44]
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  - conf/date/CherkaouiFAF12
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Abdelkarim Cherkaoui, Viktor Fischer, Alain Aubert, Laurent Fesquet:
Comparison of Self-Timed Ring and Inverter Ring Oscillators as entropy sources in FPGAs. DATE 2012: 1325-1330

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