Yusuke Matsunaga

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Taiga Takata

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Publications

2013
[j20]
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Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga:
Efficient Fault Simulation Algorithms for Analyzing Soft Error Propagation in Sequential Circuits. IPSJ Trans. Syst. LSI Des. Methodol. 6: 127-134 (2013)
2012
[j19]
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  - journals/ipsj/TakataM12
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Taiga Takata, Yusuke Matsunaga:
A Robust Algorithm for Pessimistic Analysis of Logic Masking Effects in Combinational Circuits. IPSJ Trans. Syst. LSI Des. Methodol. 5: 55-62 (2012)
2011
[c31]
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  - conf/iolts/YoshimotoAKTYMYKY11
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Shusuke Yoshimoto, Takuro Amashita, D. Kozuwa, Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure. IOLTS 2011: 151-156
[c30]
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Taiga Takata, Yusuke Matsunaga:
A robust algorithm for pessimistic analysis of logic masking effects in combinational circuits. IOLTS 2011: 246-251
2010
[c27]
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  - conf/fpga/TakataM10
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Taiga Takata, Yusuke Matsunaga:
A heuristic algorithm for LUT-based FPGA technology mapping using the lower bound for DAG covering problem (abstract only). FPGA 2010: 289
2009
[j16]
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  - journals/ieicet/TakataM09
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Taiga Takata, Yusuke Matsunaga:
Efficient Cut Enumeration Heuristics for Depth-Optimum Technology Mapping for LUT-Based FPGAs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3268-3275 (2009)
[j14]
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Taiga Takata, Yusuke Matsunaga:
Area Recovery under Depth Constraint for Technology Mapping for LUT-based FPGAs. IPSJ Trans. Syst. LSI Des. Methodol. 2: 200-211 (2009)
[c26]
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  - conf/glvlsi/TakataM09
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Taiga Takata, Yusuke Matsunaga:
An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs. ACM Great Lakes Symposium on VLSI 2009: 351-356
2008
[c24]
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  - conf/aspdac/TakataM08
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Taiga Takata, Yusuke Matsunaga:
Area recovery under depth constraint by Cut Substitution for technology mapping for LUT-based FPGAs. ASP-DAC 2008: 144-147
2006
[j5]
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  - journals/ieicet/SugiharaTNIHKHKMMO06
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Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki J. Murakami, Katsuya Okumura:
Cell Library Development Methodology for Throughput Enhancement of Character Projection Equipment. IEICE Trans. Electron. 89-C(3): 377-383 (2006)
[c20]
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  - conf/iscas/SugiharaTNIHKHKMMO06
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Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki J. Murakami, Katsuya Okumura:
A character size optimization technique for throughput enhancement of character projection lithography. ISCAS 2006
2005
[c19]
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  - conf/issoc/SugiharaTNIHKHK05
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Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki J. Murakami, Katsuya Okumura:
Cell Library Development Methodology for Throughput Enhancement of Electron Beam Direct-Write Lithography Systems. SoC 2005: 137-140

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