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H. Peter Hofstee
- > Home > Persons > H. Peter Hofstee
Publications
- 2007
- [j12]Brian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia M. Müller, Osamu Takahashi, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Shoji Onishi, Juergen Pille, Joel Silberman, Suksoon Yong, Akiyuki Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, VanDung To, Eiji Iwata:
Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI. IBM J. Res. Dev. 51(5): 529-544 (2007) - [c18]Osamu Takahashi, Erwin Behnen, Scott R. Cottier, Paula K. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, C. J. Johnson, Stephen D. Posluszny:
Cell Broadband Engine Processor Design Methodology. CICC 2007: 711-716 - 2006
- [j11]Brian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia Melitta Müller, Osamu Takahashi, A. Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, Vandung To, Eiji Iwata:
The microarchitecture of the synergistic processor for a cell processor. IEEE J. Solid State Circuits 41(1): 63-70 (2006) - 2000
- [j5]David H. Allen, Sang H. Dhong, H. Peter Hofstee, Jens Leenstra, Kevin J. Nowka, Daniel L. Stasiak, Dieter F. Wendel:
Custom circuit design as a driver of microprocessor performance. IBM J. Res. Dev. 44(6): 799-822 (2000) - [c9]Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Paula K. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, Nobuo Kojima, Ohsang Kwon, Kyung T. Lee, David Meltzer, Kevin J. Nowka, J. Park, J. Peter, Joel Silberman, Osamu Takahashi, Paul Villarrubia:
"Timing closure by design, " a high frequency microprocessor design methodology. DAC 2000: 712-717 - 1998
- [j4]Joel Silberman, Naoaki Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Axel Essbaum, Uttam Ghoshal, David F. Heidel, H. Peter Hofstee, Kyung T. Lee, David Meltzer, Hung C. Ngo, Kevin J. Nowka, Stephen D. Posluszny, Osamu Takahashi, Ivan Vo, Brian A. Zoric:
A 1.0-GHz single-issue 64-bit powerPC integer processor. IEEE J. Solid State Circuits 33(11): 1600-1608 (1998) - [j3]H. Peter Hofstee, Sang H. Dhong, David Meltzer, Kevin J. Nowka, Joel Silberman, Jeffrey L. Burns, Stephen D. Posluszny, Osamu Takahashi:
Designing for a gigahertz [guTS integer processor]. IEEE Micro 18(3): 66-74 (1998) - [c6]Osamu Takahashi, Joel Silberman, Sang H. Dhong, H. Peter Hofstee, Naoaki Aoki:
A 690 ps read-access latency register file for a GHz integer microprocessor. ICCD 1998: 6-10 - [c5]Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Uttam Ghoshal, H. Peter Hofstee, David P. LaPotin, Kyung T. Lee, David Meltzer, Hung C. Ngo, Kevin J. Nowka, Joel Silberman, Osamu Takahashi, Ivan Vo:
Design methodology for a 1.0 GHz microprocessor. ICCD 1998: 17-23 - [c4]David F. Heidel, Sang H. Dhong, H. Peter Hofstee, Michael Immediato, Kevin J. Nowka, Joel Silberman, Kevin Stawiasz:
High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz Microprocessor. VTS 1998: 234-238
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