Tomokazu Yoneda

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Thomas Edison Yu

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Publications

2010
[c28]
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Fawnizu Azmadi Hussin, Thomas Edison Yu, Tomokazu Yoneda, Hideo Fujiwara:
RedSOCs-3D: Thermal-safe test scheduling for 3D-stacked SOC. APCCAS 2010: 264-267
2009
[c23]
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Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara:
Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints. ASP-DAC 2009: 793-798
2008
[j8]
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  - journals/ieicet/YuYZF08
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Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, Hideo Fujiwara:
Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints. IEICE Trans. Inf. Syst. 91-D(3): 807-814 (2008)
[j5]
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Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara:
Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips. IEICE Trans. Inf. Syst. 91-D(10): 2440-2448 (2008)
[c21]
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Thomas Edison Yu, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara:
Identifying Non-Robust Untestable RTL Paths in Circuits with Multi-cycle Paths. ATS 2008: 125-130
2007
[c18]
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  - conf/ats/YuYCF07
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Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara:
Thermal-Safe Test Access Mechanism and Wrapper Co-optimization for System-on-Chip. ATS 2007: 187-192
[c11]
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Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, Hideo Fujiwara:
Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints. VTS 2007: 369-374

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