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Dong Xiang
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Publications
- 2018
- [j51]Dong Xiang, Krishnendu Chakrabarty, Hideo Fujiwara:
Fault-Tolerant Unicast-Based Multicast for Reliable Network-on-Chip Testing. ACM Trans. Design Autom. Electr. Syst. 23(6): 73:1-73:23 (2018) - 2016
- [j48]Dong Xiang, Krishnendu Chakrabarty, Hideo Fujiwara:
Multicast-Based Testing and Thermal-Aware Test Scheduling for 3D ICs with a Stacked Network-on-Chip. IEEE Trans. Computers 65(9): 2767-2779 (2016) - [c71]Dong Xiang, Krishnendu Chakrabarty, Hideo Fujiwara:
A unified test and fault-tolerant multicast solution for network-on-chip designs. ITC 2016: 1-9 - 2013
- [c58]Dong Xiang, Gang Liu, Krishnendu Chakrabarty, Hideo Fujiwara:
Thermal-aware test scheduling for NOC-based 3D integrated circuits. VLSI-SoC 2013: 96-101 - 2008
- [j22]Dong Xiang, Yang Zhao, Krishnendu Chakrabarty, Hideo Fujiwara:
A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals for Deterministic BIST. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(6): 999-1012 (2008) - 2007
- [j20]Dong Xiang, Kaiwei Li, Jiaguang Sun, Hideo Fujiwara:
Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction. IEEE Trans. Computers 56(4): 557-562 (2007) - [j19]Dong Xiang, Mingjing Chen, Hideo Fujiwara:
Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST. IEEE Trans. Computers 56(12): 1619-1628 (2007) - [j18]Dong Xiang, Kaiwei Li, Hideo Fujiwara, Krishnaiyan Thulasiraman, Jiaguang Sun:
Constraining Transition Propagation for Low-Power Scan Testing Using a Two-Stage Scan Architecture. IEEE Trans. Circuits Syst. II Express Briefs 54-II(5): 450-454 (2007) - [c29]Dong Xiang, Krishnendu Chakrabarty, Dianwei Hu, Hideo Fujiwara:
Scan Testing for Complete Coverage of Path Delay Faults with Reduced Test Data Volume, Test Application Time, and Hardware Cost. ATS 2007: 329-334 - [c27]Dong Xiang, Yang Zhao, Kaiwei Li, Hideo Fujiwara:
Fast and effective fault simulation for path delay faults based on selected testable paths. ITC 2007: 1-10 - 2006
- [c25]Hideo Fujiwara, Jiaguang Sun, Krishnendu Chakrabarty, Yang Zhao, Dong Xiang:
Compressing Test Data for Deterministic BIST Using a Reconfigurable Scan Arhcitecture. ATS 2006: 299-306 - [c24]Dong Xiang, Kaiwei Li, Hideo Fujiwara, Jiaguang Sun:
Generating Compact Robust and Non-Robust Tests for Complete Coverage of Path Delay Faults Based on Stuck-at Tests. ICCD 2006: 446-451 - 2005
- [j13]Dong Xiang, Ming-Jing Chen, Jia-Guang Sun, Hideo Fujiwara:
Improving test effectiveness of scan-based BIST by scan chain partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(6): 916-927 (2005) - [c22]Dong Xiang, Ming-Jing Chen, Hideo Fujiwara:
Using Weighted Scan Enable Signals to Improve the Effectiveness of Scan-Based BIST. Asian Test Symposium 2005: 126-131 - [c21]Dong Xiang, Kaiwei Li, Hideo Fujiwara:
Design for Cost Effective Scan Testing by Reconfiguring Scan Flip-Flops. Asian Test Symposium 2005: 318-323 - 2003
- [j9]Dong Xiang, Yi Xu, Hideo Fujiwara:
Nonscan Design for Testability for Synchronous Sequential Circuits Based on Conflict Resolution. IEEE Trans. Computers 52(8): 1063-1075 (2003) - [c17]Dong Xiang, Ming-Jing Chen, Jia-Guang Sun, Hideo Fujiwara:
Improving Test Quality of Scan-Based BIST by Scan Chain Partitioning. Asian Test Symposium 2003: 12-17 - [c16]Dong Xiang, Shan Gu, Hideo Fujiwara:
Non-Scan Design for Testability for Mixed RTL Circuits with Both Data Paths and Controller via Conflict Analysis. Asian Test Symposium 2003: 300-305 - 2002
- [j7]Dong Xiang, Hideo Fujiwara:
Handling the pin overhead problem of DFTs for high-quality and at-speed tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(9): 1105-1113 (2002) - [c13]Dong Xiang, Shan Gu, Hideo Fujiwara:
Non-Scan Design for Testability Based on Fault Oriented Conflict Analysis. Asian Test Symposium 2002: 86- - 2000
- [c6]Dong Xiang, Yi Xu, Hideo Fujiwara:
Non-scan design for testability for synchronous sequential circuits based on conflict analysis. ITC 2000: 520-529
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