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Rui Xiao

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Kejie Huang

> Home > Persons > Rui Xiao

Publications

2023
[j26]
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  - journals/tvlsi/XiaoZWXFSH23
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  - https://dblp.org/rec/journals/tvlsi/XiaoZWXFSH23
Rui Xiao, Yewei Zhang, Bo Wang, Yanfeng Xu, Jicong Fan, Haibin Shen, Kejie Huang:
A Low-Power In-Memory Multiplication and Accumulation Array With Modified Radix-4 Input and Canonical Signed Digit Weights. IEEE Trans. Very Large Scale Integr. Syst. 31(11): 1700-1712 (2023)
2022
[j18]
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  - journals/tcasII/ZhouHXLH22
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  - https://dblp.org/rec/journals/tcasII/ZhouHXLH22
Kaining Zhou, Yangshuo He, Rui Xiao, Jiayi Liu, Kejie Huang:
A Customized NoC Architecture to Enable Highly Localized Computing-on-the-Move DNN Dataflow. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 1692-1696 (2022)
[j16]
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  - journals/tvlsi/ZhangHXWXFS22
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Yewei Zhang, Kejie Huang, Rui Xiao, Bo Wang, Yanfeng Xu, Jicong Fan, Haibin Shen:
An 8-Bit in Resistive Memory Computing Core With Regulated Passive Neuron and Bitline Weight Mapping. IEEE Trans. Very Large Scale Integr. Syst. 30(4): 379-391 (2022)
2021
[i6]
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  - journals/corr/abs-2101-02419
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Rui Xiao, Kejie Huang, Yewei Zhang, Haibin Shen:
A Low Power In-Memory Multiplication andAccumulation Array with Modified Radix-4 Inputand Canonical Signed Digit Weights. CoRR abs/2101.02419 (2021)
[i5]
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  - journals/corr/abs-2107-09500
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Kaining Zhou, Yangshuo He, Rui Xiao, Kejie Huang:
Domino: A Tailored Network-on-Chip Architecture to Enable Highly Localized Inter- and Intra-Memory DNN Computing. CoRR abs/2107.09500 (2021)
[i4]
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  dblp key:
  - journals/corr/abs-2111-11744
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Kaining Zhou, Yangshuo He, Rui Xiao, Jiayi Liu, Kejie Huang:
A Customized NoC Architecture to Enable Highly Localized Computing-On-the-Move DNN Dataflow. CoRR abs/2111.11744 (2021)
2020
[i3]
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  - journals/corr/abs-2008-11669
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Yewei Zhang, Kejie Huang, Rui Xiao, Haibin Shen:
An 8-bit In Resistive Memory Computing Core with Regulated Passive Neuron and Bit Line Weight Mapping. CoRR abs/2008.11669 (2020)

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