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Xiang Gao 0002
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Publications
- 2015
- [c6]Xiang Gao, Eric A. M. Klumperink, Bram Nauta:
Sub-sampling PLL techniques. CICC 2015: 1-8 - 2013
- [j5]Ramen Dutta, Eric A. M. Klumperink, Xiang Gao, Zhiyu Ru, Ronan A. R. van der Zee, Bram Nauta:
Flip-Flops for Accurate Multiphase Clocking: Transmission Gate Versus Current Mode Logic. IEEE Trans. Circuits Syst. II Express Briefs 60-II(7): 422-426 (2013) - 2011
- [c5]Eric A. M. Klumperink, Ramen Dutta, Zhiyu Ru, Bram Nauta, Xiang Gao:
Jitter-Power minimization of digital frequency synthesis architectures. ISCAS 2011: 165-168 - 2010
- [j4]Xiang Gao, Eric A. M. Klumperink, Gerard Socci, Mounir Bohsali, Bram Nauta:
Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector. IEEE J. Solid State Circuits 45(9): 1809-1821 (2010) - [c4]Xiang Gao, Eric A. M. Klumperink, Gerard Socci, Mounir Bohsali, Bram Nauta:
Spur-reduction techniques for PLLs using sub-sampling phase detection. ISSCC 2010: 474-475 - 2009
- [j3]Xiang Gao, Eric A. M. Klumperink, Mounir Bohsali, Bram Nauta:
A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by N2. IEEE J. Solid State Circuits 44(12): 3253-3263 (2009) - [j2]Xiang Gao, Eric A. M. Klumperink, Paul F. J. Geraedts, Bram Nauta:
Jitter Analysis and a Benchmarking Figure-of-Merit for Phase-Locked Loops. IEEE Trans. Circuits Syst. II Express Briefs 56-II(2): 117-121 (2009) - [c2]Xiang Gao, Eric A. M. Klumperink, Mounir Bohsali, Bram Nauta:
A 2.2GHz 7.6mW sub-sampling PLL with -126dBc/Hz in-band phase noise and 0.15psrms jitter in 0.18µm CMOS. ISSCC 2009: 392-393 - 2008
- [j1]Xiang Gao, Bram Nauta, Eric A. M. Klumperink:
Advantages of Shift Registers Over DLLs for Flexible Low Jitter Multiphase Clock Generation. IEEE Trans. Circuits Syst. II Express Briefs 55-II(3): 244-248 (2008) - 2007
- [c1]Xiang Gao, Eric A. M. Klumperink, Bram Nauta:
Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers. ISCAS 2007: 2854-2857
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