Dimitri Galayko

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with François Anceau

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Publications

2019
[j10]
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Dimitri Galayko, Chuan Shan, Eldar Zianbetov, Mohammad Javidan, Anton Korniienko, François Anceau, Olivier Billoint, Éric Colinet, Elena Blokhina, Jérôme Juillard:
Synchronized Interconnected ADPLLs for Distributed Clock Generation in 65 nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs 66-II(10): 1673-1677 (2019)
2015
[c32]
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  - conf/newcas/ShanZABG15
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Chuan Shan, Eldar Zianbetov, François Anceau, Olivier Billoint, Dimitri Galayko:
A distributed synchronization of all-digital PLLs network for clock generation in synchronous SOCs. NEWCAS 2015: 1-4
2014
[c29]
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  - conf/iscas/GalaykoBZDACKJB14
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Dimitri Galayko, Elena Blokhina, Eldar Zianbetov, Andrii Dudka, François Anceau, Éric Colinet, Anton Korniienko, Jérôme Juillard, Philippe Basset:
Complexity in heterogeneous systems on chips: Dsign and analysis challenges. ISCAS 2014: 1997-2000
[c26]
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  - conf/iscas/ShanAGZ14
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Chuan Shan, François Anceau, Dimitri Galayko, Eldar Zianbetov:
"Swimming pool"-like distributed architecture for clock generation in large many-core SoC. ISCAS 2014: 2768-2771
[c25]
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  - conf/recosoc/ShanGAZ14
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Chuan Shan, Dimitri Galayko, François Anceau, Eldar Zianbetov:
A reconfigurable distributed architecture for clock generation in large many-core SoC. ReCoSoC 2014: 1-8
2013
[c24]
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  - conf/cicc/ZianbetovGAJSBKCSAJ13
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Eldar Zianbetov, Dimitri Galayko, François Anceau, Mohammad Javidan, Chuan Shan, Olivier Billoint, Anton Korniienko, Éric Colinet, Gérard Scorletti, J. M. Akrea, Jérôme Juillard:
Distributed clock generator for synchronous SoC using ADPLL network. CICC 2013: 1-4
[c21]
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  - conf/isvlsi/ShanGA13
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Chuan Shan, Dimitri Galayko, François Anceau:
On-chip clock error characterization for clock distribution system. ISVLSI 2013: 102-108
[c20]
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  - conf/reconfig/ShanZYABG13
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Chuan Shan, Eldar Zianbetov, Weiqiang Yu, François Anceau, Olivier Billoint, Dimitri Galayko:
FPGA prototyping of large reconfigurable ADPLL network for distributed clock generation. ReConFig 2013: 1-6
2012
[c17]
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  - conf/newcas/ShanGA12
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Chuan Shan, Dimitri Galayko, François Anceau:
Design and Modeling of ADPLL with sliding-window for wide range frequency tracking. NEWCAS 2012: 269-272
2011
[c14]
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  - conf/fpt/ShanZJATFGRCJ11
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Chuan Shan, Eldar Zianbetov, Mohammad Javidan, François Anceau, Mehdi Terosiet, Sylvain Feruglio, Dimitri Galayko, Olivier Romain, Éric Colinet, Jérôme Juillard:
FPGA implementation of reconfigurable ADPLL network for distributed clock generation. FPT 2011: 1-4
[c12]
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  - conf/iscas/JavidanZAGCJ11
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Mohammad Javidan, Eldar Zianbetov, François Anceau, Dimitri Galayko, Éric Colinet, Jérôme Juillard:
A novel technique to reduce the metastability of Bang-Bang Phase Frequency Detectors. ISCAS 2011: 2577-2580
[c11]
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Mohammad Javidan, Eldar Zianbetov, François Anceau, Dimitri Galayko, Anton Korniienko, Éric Colinet, Gérard Scorletti, Jean-Michel Akre, Jérôme Juillard:
All-digital PLL array provides reliable distributed clock for SOCs. ISCAS 2011: 2589-2592
[c10]
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  - conf/iscas/ZianbetovAJGCJ11
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Eldar Zianbetov, François Anceau, Mohammad Javidan, Dimitri Galayko, Éric Colinet, Jérôme Juillard:
A Digitally Controlled Oscillator in a 65-nm CMOS process for SoC clock generation. ISCAS 2011: 2845-2848

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