Marco Storace

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Tomaso Poggi

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Publications

2014
[j42]
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Matteo Rubagotti, Tomaso Poggi, Alberto Oliveri, Carlo A. Pascucci, Alberto Bemporad, Marco Storace:
Low-complexity piecewise-affine virtual sensors: theory and design. Int. J. Control 87(3): 622-632 (2014)
2012
[j37]
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  - journals/tie/PoggiRBS12
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Tomaso Poggi, Matteo Rubagotti, Alberto Bemporad, Marco Storace:
High-Speed Piecewise Affine Virtual Sensors. IEEE Trans. Ind. Electron. 59(2): 1228-1237 (2012)
[c25]
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  - conf/cdc/RubagottiPBS12
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Matteo Rubagotti, Tomaso Poggi, Alberto Bemporad, Marco Storace:
Piecewise affine direct virtual sensors with Reduced Complexity. CDC 2012: 656-661
2011
[j35]
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  - journals/ijcta/StoraceP11
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Marco Storace, Tomaso Poggi:
Digital architectures realizing piecewise-linear multivariate functions: Two FPGA implementations. Int. J. Circuit Theory Appl. 39(1): 1-15 (2011)
[j33]
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  - journals/tac/BemporadOPS11
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Alberto Bemporad, Alberto Oliveri, Tomaso Poggi, Marco Storace:
Ultra-Fast Stabilizing Model Predictive Control via Canonical Piecewise Affine Approximations. IEEE Trans. Autom. Control. 56(12): 2883-2897 (2011)
2010
[j32]
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  - journals/dsp/FedericoPJS10
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Martin Di Federico, Tomaso Poggi, Pedro Julián, Marco Storace:
Integrated circuit implementation of multi-dimensional piecewise-linear functions. Digit. Signal Process. 20(6): 1723-1732 (2010)
[j29]
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  - journals/tcas/PoggiCS10
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Tomaso Poggi, Francesco Comaschi, Marco Storace:
Digital Circuit Realization of Piecewise-Affine Functions With Nonuniform Resolution: Theory and FPGA Implementation. IEEE Trans. Circuits Syst. II Express Briefs 57-II(2): 131-135 (2010)
[c22]
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  - conf/cdc/BemporadOPS10
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Alberto Bemporad, Alberto Oliveri, Tomaso Poggi, Marco Storace:
Synthesis of stabilizing model predictive controllers via canonical piecewise affine approximations. CDC 2010: 5296-5301
[c21]
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  - conf/iscas/PoggiS10
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Tomaso Poggi, Marco Storace:
Digital architectures implementing piecewise-affine functions: An overview. ISCAS 2010: 3304-3307
2009
[c20]
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  - conf/ecctd/OliveriOPS09
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Alberto Oliveri, Andrea Oliveri, Tomaso Poggi, Marco Storace:
Circuit implementation of piecewise-affine functions based on a binary search tree. ECCTD 2009: 145-148
2007
[c17]
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  - conf/ecctd/BoggianoDPS07
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Alessio Boggiano, Simone Delfitto, Tomaso Poggi, Marco Storace:
FPGA implementation of a new scheme for the circuit realization of PWL functions. ECCTD 2007: 874-877
[c14]
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  - conf/iscas/FedericoJPS07
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Martin Di Federico, Pedro Julián, Tomaso Poggi, Marco Storace:
A Simplicial PWL Integrated Circuit Realization. ISCAS 2007: 685-688

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