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Terrence S. T. Mak

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Maurizio Palesi

> Home > Persons > Terrence S. T. Mak

Publications

2021
[j49]
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Nizar Dahir, Ammar Karkar, Maurizio Palesi, Terrence S. T. Mak, Alex Yakovlev:
Power density aware application mapping in mesh-based network-on-chip architecture: An evolutionary multi-objective approach. Integr. 81: 342-353 (2021)
[j48]
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  - journals/tc/XiaoWPSWM21
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Siyuan Xiao, Xiaohang Wang, Maurizio Palesi, Amit Kumar Singh, Liang Wang, Terrence S. T. Mak:
On Performance Optimization and Quality Control for Approximate-Communication-Enabled Networks-on-Chip. IEEE Trans. Computers 70(11): 1817-1830 (2021)
2019
[c79]
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  - conf/date/XiaoWPSM19
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Siyuan Xiao, Xiaohang Wang, Maurizio Palesi, Amit Kumar Singh, Terrence S. T. Mak:
ACDC: An Accuracy- and Congestion-aware Dynamic Traffic Control Method for Networks-on-Chip. DATE 2019: 630-633
2015
[j21]
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  - journals/cee/DaneshtalabPM15
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Masoud Daneshtalab, Maurizio Palesi, Terrence S. T. Mak:
Introduction to the special issue on NoC-based many-core architectures. Comput. Electr. Eng. 45: 359-361 (2015)
2014
[j17]
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Masoud Daneshtalab, Maurizio Palesi, Terrence S. T. Mak:
Introduction to the Special Issue on Network-on-Chip Architectures. Comput. Electr. Eng. 40(8): 257-259 (2014)
[j15]
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  - journals/tecs/WangYJ0DPM14
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Xiaohang Wang, Mei Yang, Yingtao Jiang, Peng Liu, Masoud Daneshtalab, Maurizio Palesi, Terrence S. T. Mak:
On self-tuning networks-on-chip for dynamic network-flow dominance adaptation. ACM Trans. Embed. Comput. Syst. 13(2s): 73:1-73:21 (2014)
[c51]
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  - conf/date/WangZMYJDP14
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Xiaohang Wang, Baoxin Zhao, Terrence S. T. Mak, Mei Yang, Yingtao Jiang, Masoud Daneshtalab, Maurizio Palesi:
Adaptive power allocation for many-core systems inspired from multiagent auction model. DATE 2014: 1-4
2013
[j9]
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  - journals/jsa/WangYJP0MB13
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Xiaohang Wang, Mei Yang, Yingtao Jiang, Maurizio Palesi, Peng Liu, Terrence S. T. Mak, Nader Bagherzadeh:
Efficient multicast schemes for 3-D Networks-on-Chip. J. Syst. Archit. 59(9): 693-708 (2013)
[c38]
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  - conf/nocs/WangMYJDP13
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Xiaohang Wang, Terrence S. T. Mak, Mei Yang, Yingtao Jiang, Masoud Daneshtalab, Maurizio Palesi:
On self-tuning networks-on-chip for dynamic network-flow dominance adaptation. NOCS 2013: 1-8
[e2]
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  - conf/micro/2013nocarc
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Maurizio Palesi, Terrence S. T. Mak, Masoud Daneshtalab:
Network on Chip Architectures, NoCArc '13, in conjunction with the 46th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-46, Davis, CA, USA, December 7, 2013. ACM 2013, ISBN 978-1-4503-2370-3 [contents]
2012
[j5]
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  - journals/tpds/Al-DujailyMXYP12
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Ra'ed Al-Dujaily, Terrence S. T. Mak, Fei Xia, Alex Yakovlev, Maurizio Palesi:
Embedded Transitive Closure Network for Runtime Deadlock Detection in Networks-on-Chip. IEEE Trans. Parallel Distributed Syst. 23(7): 1205-1215 (2012)
[e1]
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Maurizio Palesi, Terrence S. T. Mak:
Fifth International Workshop on Network on Chip Architectures, NoCArc '12, Vancouver, BC, Canada, December 1, 2012. ACM 2012, ISBN 978-1-4503-1540-1 [contents]
2011
[c30]
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  - conf/date/Al-DujailyMXYP11
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Ra'ed Al-Dujaily, Terrence S. T. Mak, Fei Xia, Alexandre Yakovlev, Maurizio Palesi:
Run-time deadlock detection in networks-on-chip using coupled transitive closure networks. DATE 2011: 497-502

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