Benton H. Calhoun

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Shourya Gupta

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Publications

2024
[j48]
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Shourya Gupta, Shuo Li, Benton H. Calhoun:
Scalable All-Analog LDOs With Reduced Input Offset Variability Using Digital Synthesis Flow in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 32(1): 190-194 (2024)
2022
[c120]
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Daniel S. Truesdell, Xinjian Liu, Jacob Breiholz, Shourya Gupta, Shuo Li, Benton H. Calhoun:
NanoWattch: A Self-Powered 3-nW RISC-V SoC Operable from 160mV Photovoltaic Input with Integrated Temperature Sensing and Adaptive Performance Scaling. VLSI Technology and Circuits 2022: 210-211
2021
[j39]
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Shourya Gupta, Benton H. Calhoun:
Dynamic Read V_MIN and Yield Estimation for Nanoscale SRAMs. IEEE Trans. Circuits Syst. I Regul. Pap. 68(3): 1171-1182 (2021)
[j38]
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Shourya Gupta, Benton H. Calhoun:
Dynamic Write V_MIN and Yield Estimation for Nanoscale SRAMs. IEEE Trans. Circuits Syst. I Regul. Pap. 68(12): 5038-5048 (2021)
[c117]
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  - conf/cicc/KamineniGC21
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Sumanth Kamineni, Shourya Gupta, Benton H. Calhoun:
MemGen: An Open-Source Framework for Autonomous Generation of Memory Macros. CICC 2021: 1-2
2020
[c103]
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  - conf/vlsi/AjayiKFCKGDLCSS20
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Tutu Ajayi, Sumanth Kamineni, Morteza Fayazi, Yaswanth K. Cherivirala, Kyumin Kwon, Shourya Gupta, Wenbo Duan, Jeongsup Lee, Chien-Hen Chen, Mehdi Saligane, Dennis Sylvester, David T. Blaauw, Ronald Dreslinski Jr., Benton H. Calhoun, David D. Wentzloff:
Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation. VLSI-SoC (Selected Papers) 2020: 65-85
[c102]
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  - conf/vlsi/AjayiKCFKSGCSBD20
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Tutu Ajayi, Sumanth Kamineni, Yaswanth K. Cherivirala, Morteza Fayazi, Kyumin Kwon, Mehdi Saligane, Shourya Gupta, Chien-Hen Chen, Dennis Sylvester, David T. Blaauw, Ronald G. Dreslinski, Benton H. Calhoun, David D. Wentzloff:
An Open-source Framework for Autonomous SoC Design with Analog Block Generation. VLSI-SOC 2020: 141-146
[c100]
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  - conf/vlsic/GuptaTC20
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Shourya Gupta, Daniel S. Truesdell, Benton H. Calhoun:
A 65nm 16kb SRAM with 131.5pW Leakage at 0.9V for Wireless IoT Sensor Nodes. VLSI Circuits 2020: 1-2
2019
[j32]
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  - journals/tcas/GuptaGCP19
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Shourya Gupta, Kirti Gupta, Benton H. Calhoun, Neeta Pandey:
Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(3): 978-988 (2019)

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