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Jun Yang 0006
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Publications
- 2023
- [j78]Weiwei Shan, Yuqiang Cui, Wentao Dai, Xinning Liu, Jingjing Guo, Peng Cao, Jun Yang:
An efficient path delay variability model for wide-voltage-range digital circuits. Sci. China Inf. Sci. 66(2) (2023) - [j68]Peng Cao, Guoqing He, Wenjie Ding, Zhanhua Zhang, Kai Wang, Jun Yang:
Efficient and Accurate ECO Leakage Optimization Framework With GNN and Bidirectional LSTM. IEEE Trans. Very Large Scale Integr. Syst. 31(9): 1413-1424 (2023) - 2021
- [j58]Jingjing Guo, Peng Cao, Mengxiao Li, Yu Gong, Zhiyuan Liu, Geng Bai, Jun Yang:
Semi-Analytical Path Delay Variation Model With Adjacent Gates Decorrelation for Subthreshold Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(5): 931-944 (2021) - 2020
- [c37]Jingjing Guo, Peng Cao, Mengxiao Li, Zhiyuan Liu, Jun Yang:
Statistical Timing Model for Subthreshold Circuit with Correlated Variation Consideration. ISCAS 2020: 1-5 - 2019
- [c33]Peng Cao, Jiangping Wu, Zhiyuan Liu, Jingjing Guo, Jun Yang, Longxing Shi:
A Statistical Current and Delay Model Based on Log-Skew-Normal Distribution for Low Voltage Region. ACM Great Lakes Symposium on VLSI 2019: 323-326 - [c31]Peng Cao, Zhiyuan Liu, Jiangping Wu, Jingjing Guo, Jun Yang, Longxing Shi:
A Statistical Timing Model for Low Voltage Design Considering Process Variation. ICCAD 2019: 1-8 - [c23]Peng Cao, Zhiyuan Liu, Jingjing Guo, Haoyu Pang, Jiangping Wu, Jun Yang:
Accurate and Efficient Interdependent Timing Model for Flip-Flop in Wide Voltage Region. NEWCAS 2019: 1-4 - 2017
- [j25]Chao Wang, Peng Cao, Bo Liu, Jun Yang:
Coarse-grained reconfigurable architecture with hierarchical context cache structure and management approach. IEICE Electron. Express 14(6): 20170090 (2017) - [j23]Chao Wang, Peng Cao, Jun Yang:
Efficient AES cipher on coarse-grained reconfigurable architecture. IEICE Electron. Express 14(11): 20170449 (2017) - [j21]Peng Cao, Bo Liu, Jinjiang Yang, Jun Yang, Meng Zhang, Longxing Shi:
Context Management Scheme Optimization of Coarse-Grained Reconfigurable Architecture for Multimedia Applications. IEEE Trans. Very Large Scale Integr. Syst. 25(8): 2321-2331 (2017) - 2016
- [j20]Jinjiang Yang, Ge Wei, Peng Cao, Jun Yang:
An area-efficient design of reconfigurable S-box for parallel implementation of block ciphers. IEICE Electron. Express 13(11): 20160138 (2016) - 2015
- [j17]Xinning Liu, Yuxiang Niu, Jun Yang, Peng Cao:
A GPS Bit Synchronization Method Based on Frequency Compensation. IEICE Trans. Commun. 98-B(4): 746-753 (2015) - [j16]Leibo Liu, Dong Wang, Min Zhu, Yansheng Wang, Shouyi Yin, Peng Cao, Jun Yang, Shaojun Wei:
An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding. IEEE Trans. Multim. 17(10): 1706-1720 (2015) - [j15]Leibo Liu, Dong Wang, Min Zhu, Yansheng Wang, Shouyi Yin, Peng Cao, Jun Yang, Shaojun Wei:
Correction to "An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding". IEEE Trans. Multim. 17(12): 2354-2355 (2015) - 2014
- [j13]Yansheng Wang, Leibo Liu, Shouyi Yin, Min Zhu, Peng Cao, Jun Yang, Shaojun Wei:
On-Chip Memory Hierarchy in One Coarse-Grained Reconfigurable Architecture to Compress Memory Space and to Reduce Reconfiguration Time and Data-Reference Time. IEEE Trans. Very Large Scale Integr. Syst. 22(5): 983-994 (2014) - 2013
- [j12]Yansheng Wang, Leibo Liu, Shouyi Yin, Min Zhu, Peng Cao, Jun Yang, Shaojun Wei:
Hierarchical representation of on-chip context to reduce reconfiguration time and implementation area for coarse-grained reconfigurable architecture. Sci. China Inf. Sci. 56(11): 1-20 (2013) - [j10]Hung K. Nguyen, Peng Cao, Xuexiang Wang, Jun Yang, Longxing Shi, Min Zhu, Leibo Liu, Shaojun Wei:
Hardware Software Co-design of H.264 Baseline Encoder on Coarse-Grained Dynamically Reconfigurable Computing System-on-Chip. IEICE Trans. Inf. Syst. 96-D(3): 601-615 (2013) - [j9]Gugang Gao, Peng Cao, Jun Yang, Longxing Shi:
Parallelism Analysis of H.264 Decoder and Realization on a Coarse-Grained Reconfigurable SoC. IEICE Trans. Inf. Syst. 96-D(8): 1654-1666 (2013) - [j8]Yansheng Wang, Leibo Liu, Shouyi Yin, Min Zhu, Peng Cao, Jun Yang, Shaojun Wei:
The Organization of On-Chip Data Memory in One Coarse-Grained Reconfigurable Architecture. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(11): 2218-2229 (2013) - [j6]Chen Mei, Min Li, Peng Cao, Amir Amin, Chunshu Li, Jun Yang, Antoine Dejonghe, Liesbet Van der Perre, Longxing Shi, Sofie Pollin:
Exploration of Full HD Media Decoding on a Software Defined Radio Baseband Processor. IEEE Trans. Signal Process. 61(18): 4438-4449 (2013) - 2012
- [j4]Bo Liu, Peng Cao, Min Zhu, Jun Yang, Leibo Liu, Shaojun Wei, Longxing Shi:
Reconfiguration Process Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications. IEICE Trans. Inf. Syst. 95-D(7): 1858-1871 (2012) - [c5]Chen Mei, Min Li, Peng Cao, Amir Amin, Chunshu Li, Sofie Pollin, Jun Yang:
Exploration of Full HD Media Decoding on SDR Baseband Processor. SiPS 2012: 185-190 - 2009
- [c4]Peng Cao, Chao Wang, Jun Yang, Longxing Shi:
Area-efficient line-based two-dimensional discrete wavelet transform architecture without data buffer. ICME 2009: 1094-1097
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