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ORCIDEduardo de la Torre
- > Home > Persons > Eduardo de la Torre
Publications
- 2019
[c55]Rodrigo Marino, Sergio Quintero, José Manuel Lanza-Gutiérrez, Teresa Riesgo, Miguel Holgado
, Jorge Portilla, Eduardo de la Torre:
Hardware Accelerator for Ethanol Detection in Water Media based on Machine Learning Techniques. DCIS 2019: 1-6- 2018
- [j16]Alfonso Rodríguez, Juan Valverde, Jorge Portilla, Andrés Otero, Teresa Riesgo, Eduardo de la Torre:
FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo3 Framework. Sensors 18(6): 1877 (2018) - 2016
- [j14]Teresa Cervero, Andrés Otero, Sebastián López, Eduardo de la Torre, Gustavo Marrero Callicó, Teresa Riesgo, Roberto Sarmiento:
A scalable H.264/AVC deblocking filter architecture. J. Real Time Image Process. 12(1): 81-105 (2016) - 2015
- [j11]Eduardo de la Torre, Jorge Portilla, Teresa Riesgo:
Letter from the guest editors of the special issue on DCIS 2014. Microprocess. Microsystems 39(8): 919 (2015) - [c43]Filip Veljkovic, Teresa Riesgo, Eduardo de la Torre:
Adaptive reconfigurable voting for enhanced reliability in medium-grained fault tolerant architectures. AHS 2015: 1-8 - [c42]Alfonso Rodríguez, Juan Valverde, Cesar Castanares, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo:
Live demonstration: A dynamically adaptable image processing application running in an FPGA-based WSN platform. ISCAS 2015: 1902 - [c40]Javier Mora, Andrés Otero, Eduardo de la Torre, Teresa Riesgo:
Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs. ReCoSoC 2015: 1-7 - [c38]Alfonso Rodríguez, Juan Valverde, Cesar Castanares, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo:
Execution modeling in self-aware FPGA-based architectures for efficient resource management. ReCoSoC 2015: 1-8 - 2014
- [j8]Wei He, Andrés Otero, Eduardo de la Torre, Teresa Riesgo:
Customized and automated routing repair toolset towards side-channel analysis resistant dual rail logic. Microprocess. Microsystems 38(8): 899-910 (2014) - [c37]Blanca López, Juan Valverde, Eduardo de la Torre, Teresa Riesgo:
Power-aware multi-objective evolvable hardware system on an FPGA. AHS 2014: 61-68 - [c36]Filip Veljkovic, Teresa Riesgo, Eduardo de la Torre, Raul Regada, Luis Berrojo:
A run time adaptive architecture to trade-off performance for fault tolerance applied to a DVB on-board processor. AHS 2014: 143-150 - [c35]Juan Valverde, Alfonso Rodríguez, Julio Camarero, Andrés Otero, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo:
A dynamically adaptable bus architecture for trading-off among performance, consumption and dependability in Cyber-Physical Systems. FPL 2014: 1-4 - [c33]Alfonso Rodríguez, Juan Valverde, Eduardo de la Torre, Teresa Riesgo:
Dynamic management of multikernel multithread accelerators using Dynamic Partial Reconfiguration. ReCoSoC 2014: 1-7 - 2013
- [j7]Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina:
Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing. IEEE Trans. Computers 62(8): 1481-1493 (2013) - [c32]Javier Mora, Angel Gallego, Andrés Otero, Eduardo de la Torre, Teresa Riesgo:
Noise-agnostic adaptive image filtering without training references on an evolvable hardware platform. DASIP 2013: 182-189 - [c31]Javier Mora, Angel Gallego, Andrés Otero, Blanca López, Eduardo de la Torre, Teresa Riesgo:
A noise-agnostic self-adaptive image processing application based on evolvable hardware. DASIP 2013: 351-352 - [c30]Angel Gallego, Javier Mora, Andrés Otero, Blanca López, Eduardo de la Torre, Teresa Riesgo:
A self-adaptive image processing application based on evolvable and scalable hardware. FPL 2013: 1 - [c29]Angel Gallego, Javier Mora, Andrés Otero, Rubén Salvador, Eduardo de la Torre, Teresa Riesgo:
A Novel FPGA-based Evolvable Hardware System Based on Multiple Processing Arrays. IPDPS Workshops 2013: 182-191 - [c28]Angel Gallego, Javier Mora, Andrés Otero, Eduardo de la Torre, Teresa Riesgo:
A scalable evolvable hardware processing array. ReConFig 2013: 1-7 - 2012
- [j6]Juan Valverde, Andrés Otero, Miguel Lopez, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo:
Using SRAM Based FPGAs for Power-Aware High Performance Wireless Sensor Networks. Sensors 12(3): 2667-2692 (2012) - [c27]Wei He, Eduardo de la Torre, Teresa Riesgo:
An Interleaved EPE-Immune PA-DPL Structure for Resisting Concentrated EM Side Channel Attacks on FPGA Implementation. COSADE 2012: 39-53 - [c25]Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina:
Implementation techniques for evolvable HW systems: virtual VS. dynamic reconfiguration. FPL 2012: 547-550 - [c24]Wei He, Andrés Otero, Eduardo de la Torre, Teresa Riesgo:
Automatic generation of identical routing pairs for FPGA implemented DPL logic. ReConFig 2012: 1-6 - [c23]Andrés Otero, Eduardo de la Torre, Teresa Riesgo:
Dreams: A tool for the design of dynamically reconfigurable embedded and modular systems. ReConFig 2012: 1-8 - [c22]Miguel Lombardo, Julio Camarero, Juan Valverde, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo:
Power management techniques in an FPGA-based WSN node for high performance applications. ReCoSoC 2012: 1-8 - 2011
- [c21]Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina:
Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support. AHS 2011: 184-191 - [c20]Andrés Otero, Rubén Salvador, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina:
A fast Reconfigurable 2D HW core architecture on FPGAs for evolvable Self-Adaptive Systems. AHS 2011: 336-343 - [c19]Andrés Otero, Eduardo de la Torre, Teresa Riesgo, Teresa Cervero, Sebastián López, Gustavo Marrero Callicó, Roberto Sarmiento:
Run-Time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs. FPL 2011: 369-375 - [c18]Teresa Cervero, Andrés Otero, Sebastián López, Eduardo de la Torre, Gustavo Marrero Callicó, Roberto Sarmiento, Teresa Riesgo:
A novel scalable Deblocking Filter architecture for H.264/AVC and SVC video codecs. ICME 2011: 1-6 - [c17]Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Lukás Sekanina, Teresa Riesgo:
Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware Systems. ReConFig 2011: 164-169 - [c16]Wei He, Eduardo de la Torre, Teresa Riesgo:
A Precharge-Absorbed DPL Logic for Reducing Early Propagation Effects on FPGA Implementations. ReConFig 2011: 217-222 - 2010
- [j5]Jorge Portilla, Andrés Otero, Eduardo de la Torre, Teresa Riesgo, Oliver Stecklina, Steffen Peter, Peter Langendörfer:
Adaptable Security in Wireless Sensor Networks by Using Reconfigurable ECC Hardware Coprocessors. Int. J. Distributed Sens. Networks 6(1) (2010) - [j4]Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo:
Reconfigurable Networks on Chip: DRNoC architecture. J. Syst. Archit. 56(7): 293-302 (2010) - [c15]Andrés Otero, Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo:
Generic Systolic Array for Run-Time Scalable Cores. ARC 2010: 4-16 - [c14]Andrés Otero, Angel Morales-Cas, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo:
A Modular Peripheral to Support Self-Reconfiguration in SoCs. DSD 2010: 88-95 - [c13]Andrés Otero, Eduardo de la Torre, Teresa Riesgo, Yana Esteves Krasteva:
Run-Time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs. FPL 2010: 70-76 - 2008
- [c12]Yana Esteves Krasteva, Francisco Criado, Eduardo de la Torre, Teresa Riesgo:
A Fast Emulation-Based NoC Prototyping Framework. ReConFig 2008: 211-216 - 2007
- [j3]Eduardo Peña, Eduardo de la Torre, Angel de Castro, Teresa Riesgo:
A digital system to emulate wireless networks. IET Comput. Digit. Tech. 1(5): 444-450 (2007) - [c11]Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo:
Reconfigurable Heterogeneous Communications and Core Reallocation for Dynamic HW Task Management. ISCAS 2007: 873-876 - 2006
- [j2]Jorge Portilla, Angel de Castro, Eduardo de la Torre, Teresa Riesgo:
A Modular Architecture for Nodes in Wireless Sensor Networks. J. Univers. Comput. Sci. 12(3): 328-339 (2006) - [c10]Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo, Didier Joly:
Virtex II FPGA Bitstream Manipulation: Application to Reconfiguration Control Systems. FPL 2006: 1-4 - [c9]Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo:
Partial Reconfiguration for Core Reallocation and Flexible Communications. ReCoSoC 2006: 91-97 - 2005
- [c8]Yana Esteves Krasteva, Ana B. Jimeno, Eduardo de la Torre, Teresa Riesgo:
Flexible Core Reallocation for Virtex II Structures. ERSA 2005: 189-195 - [c7]Yana Esteves Krasteva, Ana B. Jimeno, Eduardo de la Torre, Teresa Riesgo:
Straight Method for Reallocation of Complex Cores by Dynamic Reconfiguration in Virtex II FPGAs. IEEE International Workshop on Rapid System Prototyping 2005: 77-83 - 2004
- [c6]Mario García-Valderas, Eduardo de la Torre, F. Ariza, Teresa Riesgo:
Hardware and Software Debugging of FPGA Based Microprocessor Systems Through Debug Logic Insertion. FPL 2004: 1057-1061 - 2000
- [c5]Eduardo de la Torre, Teresa Riesgo, Javier Uceda, E. Macip, M. Rizzi:
Highly Configurable Control Boards: A Tool and a Design Experience. IEEE International Workshop on Rapid System Prototyping 2000: 174- - 1999
- [j1]Teresa Riesgo, Yago Torroja, Eduardo de la Torre:
Design methodologies based on hardware description languages. IEEE Trans. Ind. Electron. 46(1): 3-12 (1999) - 1998
- [c4]Teresa Riesgo, Yago Torroja, Eduardo de la Torre, Javier Uceda:
Quality Estimation of Test Vectors and Functional Validation Procedures Based on Fault and Error Models. DATE 1998: 955-956
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