Mehran Mozaffari Kermani

◀ ▶ joint publications with Ausmita Sarker

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Publications

2023
[j60]
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Ausmita Sarker, Alvaro Cintas Canto, Mehran Mozaffari Kermani, Reza Azarderakhsh:
Error Detection Architectures for Hardware/Software Co-Design Approaches of Number-Theoretic Transform. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(7): 2418-2422 (2023)
[j59]
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Alvaro Cintas Canto, Ausmita Sarker, Jasmin Kaur, Mehran Mozaffari Kermani, Reza Azarderakhsh:
Error Detection Schemes Assessed on FPGA for Multipliers in Lattice-Based Key Encapsulation Mechanisms in Post-Quantum Cryptography. IEEE Trans. Emerg. Top. Comput. 11(3): 791-797 (2023)
2022
[j52]
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Jasmin Kaur, Ausmita Sarker, Mehran Mozaffari Kermani, Reza Azarderakhsh:
Hardware Constructions for Error Detection in Lightweight Welch-Gong (WG)-Oriented Streamcipher WAGE Benchmarked on FPGA. IEEE Trans. Emerg. Top. Comput. 10(2): 1208-1215 (2022)
[j51]
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Ausmita Sarker, Mehran Mozaffari Kermani, Reza Azarderakhsh:
Efficient Error Detection Architectures for Postquantum Signature Falcon's Sampler and KEM SABER. IEEE Trans. Very Large Scale Integr. Syst. 30(6): 794-802 (2022)
2021
[j47]
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Ausmita Sarker, Mehran Mozaffari Kermani, Reza Azarderakhsh:
Fault Detection Architectures for Inverted Binary Ring-LWE Construction Benchmarked on FPGA. IEEE Trans. Circuits Syst. II Express Briefs 68(4): 1403-1407 (2021)
[j45]
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Ausmita Sarker, Mehran Mozaffari Kermani, Reza Azarderakhsh:
Error Detection Architectures for Ring Polynomial Multiplication and Modular Reduction of Ring-LWE in $\boldsymbol{\frac{\mathbb{Z}/p\mathbb{Z}[x]}{x^{n}+1}}$ Benchmarked on ASIC. IEEE Trans. Reliab. 70(1): 362-370 (2021)
2019
[j36]
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Ausmita Sarker, Mehran Mozaffari Kermani, Reza Azarderakhsh:
Hardware Constructions for Error Detection of Number-Theoretic Transform Utilized in Secure Cryptographic Architectures. IEEE Trans. Very Large Scale Integr. Syst. 27(3): 738-741 (2019)
2018
[j32]
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  - journals/tecs/KermaniASJ18
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Mehran Mozaffari Kermani, Reza Azarderakhsh, Ausmita Sarker, Amir Jalali:
Efficient and Reliable Error Detection Architectures of Hash-Counter-Hash Tweakable Enciphering Schemes. ACM Trans. Embed. Comput. Syst. 17(2): 54:1-54:19 (2018)

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