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2010 – 2019
- 2015
[j5]Chen-Yang Lin, Cheng-Chi Wong, Hsie-Chia Chang:
An Area Efficient Radix-4 Reciprocal Dual Trellis Architecture for a High-Code-Rate Turbo Decoder. IEEE Trans. Circuits Syst. II Express Briefs 62-II(1): 65-69 (2015)- 2013
- [j4]Chen-Yang Lin, Cheng-Chi Wong, Hsie-Chia Chang:
A 40 nm 535 Mbps Multiple Code-Rate Turbo Decoder Chip Using Reciprocal Dual Trellis. IEEE J. Solid State Circuits 48(11): 2662-2670 (2013) - 2011
- [j3]Cheng-Chi Wong, Hsie-Chia Chang:
High-Efficiency Processing Schedule for Parallel Turbo Decoders Using QPP Interleaver. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(6): 1412-1420 (2011) - 2010
- [j2]Cheng-Chi Wong, Ming-Wei Lai, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee:
Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture. IEEE J. Solid State Circuits 45(2): 422-432 (2010) - [j1]Cheng-Chi Wong, Hsie-Chia Chang:
Reconfigurable Turbo Decoder With Parallel Architecture for 3GPP LTE System. IEEE Trans. Circuits Syst. II Express Briefs 57-II(7): 566-570 (2010) - [c2]Chen-Yang Lin, Cheng-Chi Wong, Hsie-Chia Chang:
A multiple code-rate turbo decoder based on reciprocal dual trellis architecture. ISCAS 2010: 1496-1499
2000 – 2009
- 2007
- [c1]Cheng-Chi Wong, Cheng-Hao Tang, Ming-Wei Lai, Yan-Xiu Zheng, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee, Yu.-T. Su:
A 0.22 nJ/b/iter 0.13 μm turbo decoder chip using inter-block permutation interleaver. CICC 2007: 273-276
Coauthor Index
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