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ORCIDSamuel Bayliss
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- affiliation: Imperial College London, UK
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2020 – today
- 2020
[c16]Prasanth Chatarasi, Stephen Neuendorffer, Samuel Bayliss, Kees A. Vissers, Vivek Sarkar
:
Vyasa: A High-Performance Vectorizing Compiler for Tensor Convolutions on the Xilinx AI Engine. HPEC 2020: 1-10- [i1]Prasanth Chatarasi, Stephen Neuendorffer, Samuel Bayliss, Kees A. Vissers, Vivek Sarkar:
Vyasa: A High-Performance Vectorizing Compiler for Tensor Convolutions on the Xilinx AI Engine. CoRR abs/2006.01331 (2020)
2010 – 2019
- 2018
- [j3]Junyi Liu, John Wickerson, Samuel Bayliss, George A. Constantinides:
Polyhedral-Based Dynamic Loop Pipelining for High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(9): 1802-1815 (2018) - 2017
- [c15]Junyi Liu, John Wickerson, Samuel Bayliss, George A. Constantinides:
Run fast when you can: Loop pipelining with uncertain and non-uniform memory dependencies. ACSSC 2017: 126-130 - 2016
- [j2]Felix J. Winterstein, Samuel R. Bayliss, George A. Constantinides:
Separation Logic for High-Level Synthesis. ACM Trans. Reconfigurable Technol. Syst. 9(2): 10:1-10:23 (2016) - [c14]Nachiket Kapre, Samuel Bayliss:
Survey of domain-specific languages for FPGA computing. FPL 2016: 1-12 - 2015
- [c13]Junyi Liu, Samuel Bayliss, George A. Constantinides:
Offline Synthesis of Online Dependence Testing: Parametric Loop Pipelining for HLS. FCCM 2015: 159-162 - [c12]Felix Winterstein, Kermin Fleming, Hsin-Jung Yang, Samuel Bayliss, George A. Constantinides:
MATCHUP: Memory Abstractions for Heap Manipulating Programs. FPGA 2015: 136-145 - 2014
- [c11]Umar Ibrahim Minhas, Samuel Bayliss, George A. Constantinides:
GPU vs FPGA: A Comparative Analysis for Non-standard Precision. ARC 2014: 298-305 - [c10]Kan Shi, David Boland, Edward A. Stott, Samuel Bayliss, George A. Constantinides:
Datapath Synthesis for Overclocking: Online Arithmetic for Latency-Accuracy Trade-offs. DAC 2014: 190:1-190:6 - [c9]Felix Winterstein, Samuel Bayliss, George A. Constantinides:
Separation Logic-Assisted Code Transformations for Efficient High-Level Synthesis. FCCM 2014: 1-8 - [c8]Eduardo Aguilar-Pelaez, Samuel Bayliss, Alex I. Smith, Felix Winterstein, Dan R. Ghica, David B. Thomas, George A. Constantinides:
Compiling Higher Order Functional Programs to Composable Digital Hardware. FCCM 2014: 234 - [c7]Luca Gallo, Alessandro Cilardo, David B. Thomas, Samuel Bayliss, George A. Constantinides:
Area implications of memory partitioning for high-level synthesis on FPGAs. FPL 2014: 1-4 - 2013
- [c6]Felix Winterstein, Samuel Bayliss, George A. Constantinides:
FPGA-based K-means clustering using tree-based data structures. FPL 2013: 1-6 - [c5]Xitong Gao, Samuel Bayliss, George A. Constantinides:
SOAP: Structural optimization of arithmetic expressions for high-level synthesis. FPT 2013: 112-119 - [c4]Felix Winterstein, Samuel Bayliss, George A. Constantinides:
High-level synthesis of dynamic data structures: A case study using Vivado HLS. FPT 2013: 362-365 - 2012
- [j1]Samuel Bayliss, George A. Constantinides:
Analytical synthesis of bandwidth-efficient SDRAM address generators. Microprocess. Microsystems 36(8): 665-675 (2012) - [c3]Samuel Bayliss, George A. Constantinides:
Optimizing SDRAM bandwidth for custom FPGA loop accelerators. FPGA 2012: 195-204 - 2011
- [c2]Samuel Bayliss, George A. Constantinides:
Application Specific Memory Access, Reuse and Reordering for SDRAM. ARC 2011: 41-52
2000 – 2009
- 2006
- [c1]Samuel Bayliss, Christos-Savvas Bouganis, George A. Constantinides, Wayne Luk:
An FPGA implementation of the simplex algorithm. FPT 2006: 49-56
Coauthor Index
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