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ORCIDJorma Skyttä
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Journal Articles
- 2009
[j5]Kimmo U. Järvinen, Jorma Skyttä:
Fast point multiplication on Koblitz curves: Parallelization method and implementations. Microprocess. Microsystems 33(2): 106-116 (2009)- 2008
- [j4]Kimmo U. Järvinen, Jorma Skyttä:
On Parallelization of High-Speed Processors for Elliptic Curve Cryptography. IEEE Trans. Very Large Scale Integr. Syst. 16(9): 1162-1175 (2008) - 2001
- [j3]Mika Loukola, Jorma Skyttä:
Enhanced Augmented IP Routing Protocol (EAIRP) in IPv6 Environment. Electron. Commer. Res. 1(4): 359-370 (2001) - 1998
- [j2]Mika Loukola, Jorma Skyttä:
IPv6 over ATM flow-handling. Comput. Commun. 21(13): 1124-1130 (1998) - 1986
- [j1]Iiro Hartimo, Klaus Kronlöf, Olli Simula, Jorma Skyttä:
DFSP: A Data Flow Signal Processor. IEEE Trans. Computers 35(1): 23-33 (1986)
Conference and Workshop Papers
- 2015
- [c22]Hannu Heusala, Jorma Skyttä:
How small and still effective a CMOS-SoC could ever be? NORCAS 2015: 1-4 - 2008
- [c21]Kimmo U. Järvinen, Jorma O. Skyttä:
High-Speed Elliptic Curve Cryptography Accelerator for Koblitz Curves. FCCM 2008: 109-118 - 2007
- [c20]Kimmo U. Järvinen, Juha Forsten, Jorma Skyttä:
FPGA Design of Self-certified Signature Verification on Koblitz Curves. CHES 2007: 256-271 - 2006
- [c19]Kimmo Järvinen, Juha Forsten, Jorma Skyttä:
Efficient Circuitry for Computing τ-adic Non-Adjacent Form. ICECS 2006: 232-235 - 2005
- [c18]Kimmo U. Järvinen, Matti Tommiska, Jorma Skyttä:
A Compact MD5 and SHA-1 Co-Implementation Utilizing Algorithm Similarities. ERSA 2005: 48-54 - [c17]Kimmo U. Järvinen, Matti Tommiska, Jorma Skyttä:
Hardware Implementation Analysis of the MD5 Hash Algorithm. HICSS 2005 - 2004
- [c16]Kimmo U. Järvinen, Matti Tommiska, Jorma Skyttä:
A VHDL Generator for Elliptic Curve Cryptography. FPL 2004: 1098-1100 - [c15]Kimmo Järvinen, Matti Tommiska, Jorma Skyttä:
A scalable architecture for elliptic curve point multiplication. FPT 2004: 303-306 - [c14]Antti Hämäläinen, Matti Tommiska, Jorma Skyttä:
FPGA-Based Implementation of a 59-Neuron Feedforward Neural Network with a 17.1 Gbps Interlayer Throughput. IC-AI 2004: 181-187 - 2003
- [c13]Kimmo U. Järvinen, Matti Tommiska, Jorma Skyttä:
A fully pipelined memoryless 17.8 Gbps AES-128 encryptor. FPGA 2003: 207-215 - 2002
- [c12]Antti Hämäläinen, Matti Tommiska, Jorma Skyttä:
8 Gigabits per Second Implementation of the IDEA Cryptographic Algorithm. FPL 2002: 760-769 - 2001
- [c11]Matti Tommiska, Jorma Skyttä:
Dijkstra's Shortest Path Routing Algorithm in Reconfigurable Hardware. FPL 2001: 653-657 - [c10]Matti Tommiska, Jarno M. A. Tanskanen, Jorma O. Skyttä:
Hardware-based adaptive general parameter extension in W-CDMA power control. VTC Fall 2001: 2023-2027 - 1999
- [c9]Juha Forsten, Mika Loukola, Jorma Skyttä:
Hardware Acceleration inside a Differentiated Services Access Node. IDMS 1999: 3-16 - 1998
- [c8]Mika Loukola, Jorma Skyttä:
New Possibilities Offered by IPv6. ICCCN 1998: 548-552 - [c7]Mika Loukola, Jorma Skyttä:
Hop-by-hop option based flow-handling compared to other IP over ATM protocols. PICS 1998: 83-94 - 1996
- [c6]Jarkko Vuori, Jorma Skyttä:
Implementation of a European paging system receiver using CORDIC algorithm. EUSIPCO 1996: 1-4 - 1994
- [c5]Jarkko Vuori, J. Honkanen, Jorma Skyttä:
A new wireless paging network architecture. PIMRC 1994: 1183-1187 - 1988
- [c4]Jorma Skyttä, Tapio Takala:
A Distributed Data Model for Raytracing. Advances in Computer Graphics Hardware 1988: 19-26 - 1987
- [c3]Jorma Skyttä, Tapio Takala:
Partially Ordered Search Indices in the Organization of a Fixed Hierarchy. Advances in Computer Graphics Hardware 1987: 39-46 - 1986
- [c2]Jorma Skyttä, Tapio Takala:
Utilization of VLSI for Creating an Active Data Base of 3-D Geometric Models. Advances in Computer Graphics Hardware 1986: 83-93 - 1982
- [c1]Klaus Kronlöf, Jorma Skyttä, Iiro Hartimo, Olli Simula:
Performance of an experimental data flow architecture for signal processing. ICASSP 1982: 695-698
Coauthor Index
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