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ORCIDUlf Schlichtmann
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- affiliation: Technical University of Munich, Institute for Electronic Design Automation, Germany
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2020 – today
- 2020
[j52]Rafael Stahl
, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
Driver Generation for IoT Nodes With Optimization of the Hardware/Software Interface. IEEE Embed. Syst. Lett. 12(2): 66-69 (2020)- [j51]Johanna Baehr, Alessandro Bernardini, Georg Sigl, Ulf Schlichtmann:
Machine learning and structural characteristics for reverse engineering. Integr. 72: 1-12 (2020) - [j50]Yasamin Moradi, Mohamed Ibrahim, Krishnendu Chakrabarty, Ulf Schlichtmann:
An Efficient Fault-Tolerant Valve-Based Microfluidic Routing Fabric for Droplet Barcoding in Single-Cell Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(2): 359-372 (2020) - [j49]Qin Wang, Ulf Schlichtmann, Yici Cai, Weiqing Ji, Zeyan Li, Haena Cheong, Oh-Sun Kwon, Hailong Yao, Tsung-Yi Ho, Kwanwoo Shin, Bing Li:
Integrated Control-Fluidic Codesign Methodology for Paper-Based Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(3): 613-625 (2020) - [j48]Ying Zhu, Xing Huang, Bing Li, Tsung-Yi Ho, Qin Wang, Hailong Yao, Robert Wille, Ulf Schlichtmann:
Multicontrol: Advanced Control-Logic Synthesis for Flow-Based Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2489-2502 (2020) - [j47]Chunfeng Liu, Bing Li, Bhargab B. Bhattacharya, Krishnendu Chakrabarty, Tsung-Yi Ho, Ulf Schlichtmann:
Test Generation for Flow-Based Microfluidic Biochips With General Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2530-2543 (2020) - [c158]Shuhang Zhang, Grace Li Zhang, Bing Li, Hai Helen Li, Ulf Schlichtmann:
Lifetime Enhancement for RRAM-based Computing-In-Memory Engine Considering Aging and Thermal Effects. AICAS 2020: 11-15 - [c157]Uzair Sharif, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
Investigating the Inherent Soft Error Resilience of Embedded Applications by Full-System Simulation. ASP-DAC 2020: 80-84 - [c156]Mengchu Li, Tsun-Ming Tseng, Mahdi Tala, Ulf Schlichtmann:
Maximizing the Communication Parallelism for Wavelength-Routed Optical Networks-On-Chips. ASP-DAC 2020: 109-114 - [c155]Grace Li Zhang, Michaela Brunner, Bing Li, Georg Sigl, Ulf Schlichtmann:
Timing Resilience for Efficient and Secure Circuits. ASP-DAC 2020: 623-628 - [c154]Gautam Choudhary, Sandeep Pal, Debraj Kundu, Sukanta Bhattacharjee, Shigeru Yamashita, Bing Li, Ulf Schlichtmann, Sudip Roy:
Transport-Free Module Binding for Sample Preparation using Microfluidic Fully Programmable Valve Arrays. DATE 2020: 1335-1338 - [c153]Shuhang Zhang, Bing Li, Hai Helen Li, Ulf Schlichtmann:
A Pulse-width Modulation Neuron with Continuous Activation for Processing-In-Memory Engines. DATE 2020: 1426-1431 - [c152]Ying Zhu, Grace Li Zhang, Tianchen Wang, Bing Li, Yiyu Shi, Tsung-Yi Ho, Ulf Schlichtmann:
Statistical Training for Neuromorphic Computing using Memristor-based Crossbars Considering Process Variations and Noise. DATE 2020: 1590-1593 - [c151]Grace Li Zhang, Bing Li, Ying Zhu, Shuhang Zhang, Tianchen Wang, Yiyu Shi, Tsung-Yi Ho, Hai (Helen) Li, Ulf Schlichtmann:
Reliable and Robust RRAM-based Neuromorphic Computing. ACM Great Lakes Symposium on VLSI 2020: 33-38 - [c150]Marcel Mettler, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
Runtime Monitoring of Inter- and Intra-Thread Requirements on Embedded MPSoCs. VLSI Design 2020: 49-54 - [i24]Grace Li Zhang, Bing Li, Meng Li, Bei Yu, David Z. Pan, Michaela Brunner, Georg Sigl, Ulf Schlichtmann:
TimingCamouflage+: Netlist Security Enhancement with Unconventional Timing (with Appendix). CoRR abs/2003.00862 (2020) - [i23]Felix Last, Max Haeberlein, Ulf Schlichtmann:
Predicting Memory Compiler Performance Outputs using Feed-Forward Neural Networks. CoRR abs/2003.03269 (2020)
2010 – 2019
- 2019
- [j46]Grace Li Zhang, Bing Li, Yiyu Shi, Jiang Hu, Ulf Schlichtmann:
EffiTest2: Efficient Delay Test and Prediction for Post-Silicon Clock Skew Configuration Under Process Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(4): 705-718 (2019) - [j45]Mohamed Ibrahim, Krishnendu Chakrabarty, Ulf Schlichtmann:
Synthesis of a Cyberphysical Hybrid Microfluidic Platform for Single-Cell Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(7): 1237-1250 (2019) - [j44]Mohamed Ibrahim, Aditya Sridhar, Krishnendu Chakrabarty, Ulf Schlichtmann:
Synthesis of Reconfigurable Flow-Based Biochips for Scalable Single-Cell Screening. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(12): 2255-2270 (2019) - [c149]Petra R. Kleeberger, Juana Rivera, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
SeRoHAL: generation of selectively robust hardware abstraction layers for efficient protection of mixed-criticality systems. ASP-DAC 2019: 33-38 - [c148]Johanna Baehr, Alessandro Bernardini, Georg Sigl, Ulf Schlichtmann:
Machine learning and structural characteristics for reverse engineering. ASP-DAC 2019: 96-103 - [c147]Xing Huang, Tsung-Yi Ho, Wenzhong Guo, Bing Li, Ulf Schlichtmann:
MiniControl: Synthesis of Continuous-Flow Microfluidics with Strictly Constrained Control Ports. DAC 2019: 145 - [c146]Michael Schwarz, Raphael Stahl, Daniel Müller-Gritschneder, Ulf Schlichtmann, Dominik Stoffel, Wolfgang Kunz:
ACCESS: HW/SW Co-Equivalence Checking for Firmware Optimization. DAC 2019: 187 - [c145]Eric Cheng, Daniel Mueller-Gritschneder, Jacob A. Abraham, Pradip Bose, Alper Buyuktosunoglu, Deming Chen, Hyungmin Cho, Yanjing Li, Uzair Sharif, Kevin Skadron, Mircea Stan, Ulf Schlichtmann, Subhasish Mitra:
Cross-Layer Resilience: Challenges, Insights, and the Road Ahead. DAC 2019: 198 - [c144]Tim Fritzmann, Uzair Sharif, Daniel Müller-Gritschneder, Cezar Reinbrecht, Ulf Schlichtmann, Johanna Sepúlveda:
Towards Reliable and Secure Post-Quantum Co-Processors based on RISC-V. DATE 2019: 1148-1153 - [c143]Alexandra Listl, Daniel Mueller-Gritschneder, Ulf Schlichtmann, Sani R. Nassif:
SRAM Design Exploration with Integrated Application-Aware Aging Analysis. DATE 2019: 1249-1252 - [c142]Zhisheng Chen, Xing Huang, Wenzhong Guo, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann:
Physical Synthesis of Flow-Based Microfluidic Biochips Considering Distributed Channel Storage. DATE 2019: 1525-1530 - [c141]Yu-Huei Lin, Tsung-Yi Ho, Bing Li, Ulf Schlichtmann:
Block-Flushing: A Block-based Washing Algorithm for Programmable Microfluidic Devices. DATE 2019: 1531-1536 - [c140]Alessandro Bernardini, Chunfeng Liu, Bing Li, Ulf Schlichtmann:
Fault Localization in Programmable Microfluidic Devices. DATE 2019: 1607-1610 - [c139]Shuhang Zhang, Grace Li Zhang, Bing Li, Hai Helen Li, Ulf Schlichtmann:
Aging-aware Lifetime Enhancement for Memristor-based Neuromorphic Computing. DATE 2019: 1751-1756 - [c138]Mengchu Li, Tsun-Ming Tseng, Yanlu Ma, Tsung-Yi Ho, Ulf Schlichtmann:
VOM: Flow-Path Validation and Control-Sequence Optimization for Multilayered Continuous-Flow Microfluidic Biochips. ICCAD 2019: 1-8 - [c137]Ulf Schlichtmann, Sabya Das, Ing-Chao Lin, Mark Po-Hung Lin:
Overview of 2019 CAD Contest at ICCAD. ICCAD 2019: 1-2 - [c136]Tsun-Ming Tseng, Mengchu Li, Yushen Zhang, Tsung-Yi Ho, Ulf Schlichtmann:
Cloud Columba: Accessible Design Automation Platform for Production and Inspiration: Invited Paper. ICCAD 2019: 1-6 - [c135]Tsun-Ming Tseng, Alexandre Truppel, Mengchu Li, Mahdi Nikdast, Ulf Schlichtmann:
Wavelength-Routed Optical NoCs: Design and EDA - State of the Art and Future Directions: Invited Paper. ICCAD 2019: 1-6 - [c134]Alexandre Truppel, Tsun-Ming Tseng, Davide Bertozzi, José Carlos Alves, Ulf Schlichtmann:
PSION: Combining Logical Topology and Physical Layout Optimization for Wavelength-Routed ONoCs. ISPD 2019: 49-56 - [c133]Xu Liu, Alessandro Bernardini, Ulf Schlichtmann, Xing Zhou:
A Compact Model of Negative Bias Temperature Instability Suitable for Gate-Level Circuit Simulation. ISQED 2019: 76-80 - [c132]Alexandra Listl, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
MAGIC: A Wear-leveling Circuitry to Mitigate Aging Effects in Sense Amplifiers of SRAMs. NEWCAS 2019: 1-4 - [c131]Rafael Stahl, Zhuoran Zhao, Daniel Mueller-Gritschneder, Andreas Gerstlauer, Ulf Schlichtmann:
Fully Distributed Deep Learning Inference on Resource-Constrained Edge Devices. SAMOS 2019: 77-90 - [i22]Krishnendu Chakrabarty, Tsung-Yi Ho, Hai Li, Ulf Schlichtmann:
Emerging Hardware Techniques and EDA Methodologies for Neuromorphic Computing (Dagstuhl Seminar 19152). Dagstuhl Reports 9(4): 43-58 (2019) - 2018
- [j43]Bing Li, Masanori Hashimoto, Ulf Schlichtmann:
From Process Variations to Reliability: A Survey of Timing of Digital Circuits in the Nanometer Era. IPSJ Trans. Syst. LSI Des. Methodol. 11 (2018) - [j42]Alessandro Bernardini, Chunfeng Liu, Bing Li, Ulf Schlichtmann:
Efficient spanning-tree-based test pattern generation for Programmable Microfluidic Devices. Microelectron. J. 79: 38-45 (2018) - [j41]Grace Li Zhang, Bing Li, Jinglan Liu, Yiyu Shi, Ulf Schlichtmann:
Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(2): 392-405 (2018) - [j40]Tsun-Ming Tseng, Mengchu Li, Daniel Nestor Freitas, Travis McAuley, Bing Li, Tsung-Yi Ho, Ismail Emre Araci, Ulf Schlichtmann:
Columba 2.0: A Co-Layout Synthesis Tool for Continuous-Flow Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(8): 1588-1601 (2018) - [j39]Petra R. Maier, Veit B. Kleeberger, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
Fault Injection for Test-Driven Development of Robust SoC Firmware. ACM Trans. Embed. Comput. Syst. 17(1): 19:1-19:26 (2018) - [j38]Munish Jassi, Yong Hu, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
Graph-Grammar-Based IP-Integration (GRIP) - An EDA Tool for Software-Defined SoCs. ACM Trans. Design Autom. Electr. Syst. 23(3): 40:1-40:26 (2018) - [j37]Dimo Martev, Sven Hampel, Ulf Schlichtmann:
Automated Phase-Noise-Aware Design of RF Clock Distribution Circuits. IEEE Trans. Very Large Scale Integr. Syst. 26(11): 2395-2405 (2018) - [c130]Daniel Tille, Benedikt Gottinger, Ulrike Pfannkuchen, Helmut Graeb, Ulf Schlichtmann:
On enabling diagnosis for 1-Pin Test fails in an industrial flow. ASP-DAC 2018: 233-238 - [c129]Grace Li Zhang, Bing Li, Masanori Hashimoto, Ulf Schlichtmann:
Virtualsync: timing optimization by synchronizing logic waves with sequential and combinational components as delay units. DAC 2018: 26:1-26:6 - [c128]Yu-Kai Chuang, Kuan-Jung Chen, Kun-Lin Lin, Shao-Yun Fang, Bing Li, Ulf Schlichtmann:
PlanarONoC: concurrent placement and routing considering crossing minimization for optical networks-on-chip. DAC 2018: 151:1-151:6 - [c127]Tsun-Ming Tseng, Mengchu Li, Daniel Nestor Freitas, Amy Mongersun, Ismail Emre Araci, Tsung-Yi Ho, Ulf Schlichtmann:
Columba S: a scalable co-layout design automation tool for microfluidic large-scale integration. DAC 2018: 163:1-163:6 - [c126]Chunfeng Liu, Bing Li, Tsung-Yi Ho, Krishnendu Chakrabarty, Ulf Schlichtmann:
Design-for-testability for continuous-flow microfluidic biochips. DAC 2018: 164:1-164:6 - [c125]Grace Li Zhang, Bing Li, Bei Yu, David Z. Pan, Ulf Schlichtmann:
TimingCamouflage: Improving circuit security against counterfeiting by unconventional timing. DATE 2018: 91-96 - [c124]Daniel Mueller-Gritschneder, Martin Dittrich, Josef Weinzierl, Eric Cheng, Subhasish Mitra, Ulf Schlichtmann:
ETISS-ML: A multi-level instruction set simulator with RTL-level fault injection support for the evaluation of cross-layer resiliency techniques. DATE 2018: 609-612 - [c123]Yasamin Moradi, Mohamed Ibrahim, Krishnendu Chakrabarty, Ulf Schlichtmann:
Fault-tolerant valve-based microfluidic routing fabric for droplet barcoding in single-cell analysis. DATE 2018: 1484-1487 - [c122]Yasamin Moradi, Krishnendu Chakrabarty, Ulf Schlichtmann:
An efficient fault-tolerant valve-based microfluidic routing fabric for single-cell analysis. ETS 2018: 1-2 - [c121]Rafael Stahl, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
Automated Redirection of Hardware Accesses for Host-Compiled Software Simulation. FDL 2018: 5-16 - [c120]Robert Wille, Bing Li, Rolf Drechsler, Ulf Schlichtmann:
Automatic Design of Microfluidic Devices. FDL 2018: 5-16 - [c119]Mengchu Li, Tsun-Ming Tseng, Davide Bertozzi, Mahdi Tala, Ulf Schlichtmann:
CustomTopo: a topology generation method for application-specific wavelength-routed optical NoCs. ICCAD 2018: 100 - [c118]Yong Hu, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
Wavefront-MCTS: multi-objective design space exploration of NoC architectures based on Monte Carlo tree search. ICCAD 2018: 102 - [c117]Ying Zhu, Bing Li, Tsung-Yi Ho, Qin Wang, Hailong Yao, Robert Wille, Ulf Schlichtmann:
Multi-channel and fault-tolerant control multiplexing for flow-based microfluidic biochips. ICCAD 2018: 123 - [c116]Daniel Mueller-Gritschneder, Uzair Sharif, Ulf Schlichtmann:
Performance and accuracy in soft-error resilience evaluation using the multi-level processor simulator ETISS-ML. ICCAD 2018: 127 - [c115]Chunfeng Liu, Bing Li, Bhargab B. Bhattacharya, Krishnendu Chakrabarty, Tsung-Yi Ho, Ulf Schlichtmann:
Test generation for microfluidic fully programmable valve arrays (FPVAs) with heuristic acceleration. ICICDT 2018: 97-100 - [c114]Petra R. Maier, Uzair Sharif, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
Efficient Fault Injection for Embedded Systems: As Fast as Possible but as Accurate as Necessary. IOLTS 2018: 119-122 - [c113]Alexandra Listl, Daniel Mueller-Gritschneder, Fabian Kluge, Ulf Schlichtmann:
Emulation of an ASIC Power, Temperature and Aging Monitor System for FPGA Prototyping. IOLTS 2018: 220-225 - [c112]Fengxian Jiao, Sheqin Dong, Bei Yu, Bing Li, Ulf Schlichtmann:
Thermal-Aware Placement and Routing for 3D Optical Networks-on-Chips. ISCAS 2018: 1-4 - [c111]Grace Li Zhang, Bing Li, Ulf Schlichtmann:
Timing with Virtual Signal Synchronization for Circuit Performance and Netlist Security. ISVLSI 2018: 715-718 - 2017
- [j36]Elisabeth Glocker, Qingqing Chen, Ulf Schlichtmann, Doris Schmitt-Landsiedel:
Emulation of an ASIC power and temperature monitoring system (eTPMon) for FPGA prototyping. Microprocess. Microsystems 50: 90-101 (2017) - [j35]Qin Wang, Yue Xu, Shiliang Zuo, Hailong Yao, Tsung-Yi Ho, Bing Li, Ulf Schlichtmann, Yici Cai:
Pressure-Aware Control Layer Optimization for Flow-Based Microfluidic Biochips. IEEE Trans. Biomed. Circuits Syst. 11(6): 1488-1499 (2017) - [j34]Tsun-Ming Tseng, Bing Li, Ching-Feng Yeh, Hsiang-Chieh Jhan, Zuo-Min Tsai, Mark Po-Hung Lin, Ulf Schlichtmann:
An Efficient Two-Phase ILP-Based Algorithm for Precise CMOS RFIC Layout Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(8): 1313-1326 (2017) - [c110]Qin Wang, Shiliang Zuo, Hailong Yao, Tsung-Yi Ho, Bing Li, Ulf Schlichtmann, Yici Cai:
Hamming-distance-based valve-switching optimization for control-layer multiplexing in flow-based microfluidic biochips. ASP-DAC 2017: 524-529 - [c109]Chunfeng Liu, Bing Li, Hailong Yao, Paul Pop, Tsung-Yi Ho, Ulf Schlichtmann:
Transport or Store?: Synthesizing Flow-based Microfluidic Biochips using Distributed Channel Storage. DAC 2017: 49:1-49:6 - [c108]Mengchu Li, Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann:
Component-Oriented High-level Synthesis for Continuous-Flow Microfluidics Considering Hybrid-Scheduling. DAC 2017: 51:1-51:6 - [c107]Chunfeng Liu, Bing Li, Bhargab B. Bhattacharya, Krishnendu Chakrabarty, Tsung-Yi Ho, Ulf Schlichtmann:
Testing microfluidic Fully Programmable Valve Arrays (FPVAs). DATE 2017: 91-96 - [c106]Mohamed Ibrahim, Krishnendu Chakrabarty, Ulf Schlichtmann:
CoSyn: Efficient single-cell analysis using a hybrid microfluidic platform. DATE 2017: 1673-1678 - [c105]Bing Li, Ulf Schlichtmann:
Reliability-aware synthesis and fault test of fully programmable valve arrays (FPVAs). DFT 2017: 1 - [c104]Dimo Martev, Sven Hampel, Ulf Schlichtmann:
A Method for Phase Noise Analysis of RF Circuits. ACM Great Lakes Symposium on VLSI 2017: 227-231 - [c103]Yong Hu, Daniel Müller-Gritschneder, Ulf Schlichtmann:
Model-based framework for networks-on-chip design space exploration. AISTECS@HiPEAC 2017: 32-35 - [c102]Mohamed Ibrahim, Aditya Sridhar, Krishnendu Chakrabarty, Ulf Schlichtmann:
Sortex: Efficient timing-driven synthesis of reconfigurable flow-based biochips for scalable single-cell screening. ICCAD 2017: 623-630 - [c101]Dimo Martev, Sven Hampel, Ulf Schlichtmann:
Methodology for automated phase noise minimization in RF circuit interconnect trees. ISCAS 2017: 1-4 - [c100]Daniel Mueller-Gritschneder, Keerthikumara Devarajegowda, Martin Dittrich, Wolfgang Ecker, Marc Greim, Ulf Schlichtmann:
The extendable translating instruction set simulator (ETISS) interlinked with an MDA framework for fast RISC prototyping. RSP 2017: 79-84 - [c99]Ulf Schlichtmann:
Frontiers of timing. SLIP 2017: 1-4 - [c98]Shushanik Karapetyan, Ulf Schlichtmann:
20nm FinFET-based SRAM cell: Impact of variability and design choices on performance characteristics. SMACD 2017: 1-4 - [c97]Jinglan Liu, Yukun Ding, Jianlei Yang, Ulf Schlichtmann, Yiyu Shi:
Generative adversarial network based scalable on-chip noise sensor placement. SoCC 2017: 239-242 - [c96]Baris Yigit, Grace Li Zhang, Bing Li, Yiyu Shi, Ulf Schlichtmann:
Application of machine learning methods in post-silicon yield improvement. SoCC 2017: 243-248 - [e1]Massimo Alioto, Hai Helen Li, Jürgen Becker, Ulf Schlichtmann, Ramalingam Sridhar:
30th IEEE International System-on-Chip Conference, SOCC 2017, Munich, Germany, September 5-8, 2017. IEEE 2017, ISBN 978-1-5386-4034-0 [contents] - [i21]Bing Li, Christoph Knoth, Walter Schneider, Manuel Schmidt, Ulf Schlichtmann:
Static Timing Model Extraction for Combinational Circuits. CoRR abs/1705.02610 (2017) - [i20]Bing Li, Ning Chen, Manuel Schmidt, Walter Schneider, Ulf Schlichtmann:
On Hierarchical Statistical Static Timing Analysis. CoRR abs/1705.04975 (2017) - [i19]Bing Li, Ning Chen, Ulf Schlichtmann:
Timing Model Extraction for Sequential Circuits Considering Process Variations. CoRR abs/1705.04976 (2017) - [i18]Bing Li, Ning Chen, Ulf Schlichtmann:
Fast Statistical Timing Analysis for Circuits with Post-Silicon Tunable Clock Buffers. CoRR abs/1705.04979 (2017) - [i17]Bing Li, Ning Chen, Ulf Schlichtmann:
Statistical Timing Analysis for Latch-Controlled Circuits with Reduced Iterations and Graph Transformations. CoRR abs/1705.04980 (2017) - [i16]Bing Li, Ning Chen, Yang Xu, Ulf Schlichtmann:
On Timing Model Extraction and Hierarchical Statistical Timing Analysis. CoRR abs/1705.04981 (2017) - [i15]Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann:
Post-Route Refinement for High-Frequency PCBs Considering Meander Segment Alleviation. CoRR abs/1705.04982 (2017) - [i14]Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann:
Post-Route Alleviation of Dense Meander Segments in High-Performance Printed Circuit Boards. CoRR abs/1705.04983 (2017) - [i13]Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann:
ILP-based Alleviation of Dense Meander Segments with Prioritized Shifting and Progressive Fixing in PCB Routing. CoRR abs/1705.04984 (2017) - [i12]Bing Li, Ulf Schlichtmann:
Statistical Timing Analysis and Criticality Computation for Circuits with Post-Silicon Clock Tuning Elements. CoRR abs/1705.04986 (2017) - [i11]Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann:
Storage and Caching: Synthesis of Flow-based Microfluidic Biochips. CoRR abs/1705.04988 (2017) - [i10]Grace Li Zhang, Bing Li, Ulf Schlichtmann:
Sampling-based Buffer Insertion for Post-Silicon Yield Improvement under Process Variability. CoRR abs/1705.04990 (2017) - [i9]Tsun-Ming Tseng, Bing Li, Ching-Feng Yeh, Hsiang-Chieh Jhan, Zuo-Min Tsai, Mark Po-Hung Lin, Ulf Schlichtmann:
Novel CMOS RFIC Layout Generation with Concurrent Device Placement and Fixed-Length Microstrip Routing. CoRR abs/1705.04991 (2017) - [i8]Grace Li Zhang, Bing Li, Ulf Schlichtmann:
EffiTest: Efficient Delay Test and Statistical Prediction for Configuring Post-silicon Tunable Buffers. CoRR abs/1705.04992 (2017) - [i7]Grace Li Zhang, Bing Li, Ulf Schlichtmann:
PieceTimer: A Holistic Timing Analysis Framework Considering Setup/Hold Time Interdependency Using A Piecewise Model. CoRR abs/1705.04993 (2017) - [i6]Grace Li Zhang, Bing Li, Jinglan Liu, Yiyu Shi, Ulf Schlichtmann:
Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning. CoRR abs/1705.04995 (2017) - [i5]Chunfeng Liu, Bing Li, Bhargab B. Bhattacharya, Krishnendu Chakrabarty, Tsung-Yi Ho, Ulf Schlichtmann:
Testing Microfluidic Fully Programmable Valve Arrays (FPVAs). CoRR abs/1705.04996 (2017) - [i4]Chunfeng Liu, Bing Li, Hailong Yao, Paul Pop, Tsung-Yi Ho, Ulf Schlichtmann:
Transport or Store? Synthesizing Flow-based Microfluidic Biochips using Distributed Channel Storage. CoRR abs/1705.04998 (2017) - 2016
- [j33]Santiago Pagani, Lars Bauer, Qingqing Chen, Elisabeth Glocker, Frank Hannig, Andreas Herkersdorf, Heba Khdr, Anuj Pathania, Ulf Schlichtmann, Doris Schmitt-Landsiedel, Mark Sagi, Éricles Rodrigues Sousa, Philipp Wagner, Volker Wenzel, Thomas Wild, Jörg Henkel:
Dark silicon management: an integrated and coordinated cross-layer approach. it Inf. Technol. 58(6): 297-307 (2016) - [j32]Anja von Beuningen, Luca Ramini, Davide Bertozzi, Ulf Schlichtmann:
PROTON+: A Placement and Routing Tool for 3D Optical Networks-on-Chip with a Single Optical Layer. ACM J. Emerg. Technol. Comput. Syst. 12(4): 44:1-44:28 (2016) - [j31]Asen Asenov, Ulf Schlichtmann, Cher Ming Tan, Hei Wong, Xing Zhou:
Editorial. Microelectron. Reliab. 61: 1-2 (2016) - [j30]Shushanik Karapetyan, Veit Kleeberger, Ulf Schlichtmann:
FinFET-based product performance: Modeling and evaluation of standard cells in FinFET technologies. Microelectron. Reliab. 61: 30-34 (2016) - [j29]André Lange, Christoph Sohrmann, Roland Jancke, Joachim Haase, Binjie Cheng, Asen Asenov, Ulf Schlichtmann:
Multivariate Modeling of Variability Supporting Non-Gaussian and Correlated Parameters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(2): 197-210 (2016) - [j28]Tsun-Ming Tseng, Bing Li, Mengchu Li, Tsung-Yi Ho, Ulf Schlichtmann:
Reliability-Aware Synthesis With Dynamic Device Mapping and Fluid Routing for Flow-Based Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(12): 1981-1994 (2016) - [c95]Ulf Schlichtmann, Masanori Hashimoto, Iris Hui-Ru Jiang, Bing Li:
Reliability, adaptability and flexibility in timing: Buy a life insurance for your circuits. ASP-DAC 2016: 705-711 - [c94]Petra R. Maier, Veit Kleeberger, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
Fault injection at host-compiled level with static fault set reduction for SoC firmware robustness testing. CODES+ISSS 2016: 18:1-18:10 - [c93]Grace Li Zhang, Bing Li, Ulf Schlichtmann:
EffiTest: efficient delay test and statistical prediction for configuring post-silicon tunable buffers. DAC 2016: 60:1-60:6 - [c92]Tsun-Ming Tseng, Bing Li, Ching-Feng Yeh, Hsiang-Chieh Jhan, Zuo-Min Tsai, Mark Po-Hung Lin, Ulf Schlichtmann:
Novel CMOS RFIC layout generation with concurrent device placement and fixed-length microstrip routing. DAC 2016: 101:1-101:6 - [c91]Tsun-Ming Tseng, Mengchu Li, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann:
Columba: co-layout synthesis for continuous-flow microfluidic biochips. DAC 2016: 147:1-147:6 - [c90]Mengchu Li, Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann:
Sieve-valve-aware synthesis of flow-based microfluidic biochips considering specific biological execution limitations. DATE 2016: 624-629 - [c89]Grace Li Zhang, Bing Li, Ulf Schlichtmann:
Sampling-based buffer insertion for post-silicon yield improvement under process variability. DATE 2016: 1457-1460 - [c88]Dimo Martev, Sven Hampel, Ulf Schlichtmann:
Fully synthesized time-to-digital converter for cellular transceivers. EBCCSP 2016: 1-5 - [c87]Munish Jassi, Uzair Sharif, Daniel Müller-Gritschneder, Ulf Schlichtmann:
Hardware-Accelerated Software Library Drivers Generation for IP-Centric SoC Designs. ACM Great Lakes Symposium on VLSI 2016: 287-292 - [c86]Alessandro Bernardini, Wolfgang Ecker, Ulf Schlichtmann:
Where formal verification can help in functional safety analysis. ICCAD 2016: 85 - [c85]Grace Li Zhang, Bing Li, Ulf Schlichtmann:
PieceTimer: a holistic timing analysis framework considering setup/hold time interdependency using a piecewise model. ICCAD 2016: 100 - [c84]Qin Wang, Zeyan Li, Haena Cheong, Oh-Sun Kwon, Hailong Yao, Tsung-Yi Ho, Kwanwoo Shin, Bing Li, Ulf Schlichtmann, Yici Cai:
Control-fluidic CoDesign for paper-based digital microfluidic biochips. ICCAD 2016: 103 - [c83]