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Jun Jin Kong
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2020 – today
- 2021
- [j5]Ki Chul Chun
, Yong-Ki Kim
, Yesin Ryu, Jaewon Park, Chi Sung Oh
, Young-Yong Byun, So-Young Kim, Dong-Hak Shin, Jun Gyu Lee, Byung-Kyu Ho, Min-Sang Park, Seong-Jin Cho, Seunghan Woo, Byoung-Mo Moon, Beomyong Kil, Sungoh Ahn, Jae Hoon Lee, Sooyoung Kim, Seouk-Kyu Choi, Jae-Seung Jeong, Sung-Gi Ahn, Jihye Kim, Jun Jin Kong, Kyomin Sohn
, Nam Sung Kim, Jung-Bae Lee:
A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme. IEEE J. Solid State Circuits 56(1): 199-211 (2021) - 2020
- [c6]Chi-Sung Oh, Ki Chul Chun, Young-Yong Byun, Yong-Ki Kim, So-Young Kim, Yesin Ryu, Jaewon Park, Sinho Kim, Sang-uhn Cha, Dong-Hak Shin, Jungyu Lee, Jong-Pil Son, Byung-Kyu Ho, Seong-Jin Cho, Beomyong Kil, Sungoh Ahn, Baekmin Lim, Yong-Sik Park, Kijun Lee, Myung-Kyu Lee, Seungduk Baek, Junyong Noh, Jae-Wook Lee, Seungseob Lee, Sooyoung Kim, Bo-Tak Lim, Seouk-Kyu Choi, Jin-Guk Kim, Hye-In Choi, Hyuk-Jun Kwon, Jun Jin Kong, Kyomin Sohn, Nam Sung Kim, Kwang-Il Park, Jung-Bae Lee:
22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme. ISSCC 2020: 330-332
2010 – 2019
- 2018
- [j4]Jaeyong Son, Jun Jin Kong, Kyeongcheol Yang:
Efficient decoding of block turbo codes. J. Commun. Networks 20(4): 345-353 (2018) - 2016
- [c5]Sung-Rae Kim, Kijun Lee, Gyuyeol Kong, Myung-Kyu Lee, Dongmin Shin, Geunyeong Yu, Beomkyu Shin, Pilsang Yoon, Hongrak Son, Jun Jin Kong:
A post-processing algorithm for reducing strong error effects in NAND flash memory. APCCAS 2016: 465-468 - 2013
- [c4]Yongjune Kim
, B. V. K. Vijaya Kumar
, Kyoung Lae Cho, Hongrak Son, Jaehong Kim, Jun Jin Kong, Jaejin Lee:
Modulation coding for flash memories. ICNC 2013: 961-967 - [i1]Yongjune Kim, Kyoung Lae Cho, Hongrak Son, Jaehong Kim, Jun Jin Kong, Jaejin Lee, B. V. K. Vijaya Kumar:
Modulation Coding for Flash Memories. CoRR abs/1304.4811 (2013) - 2012
- [j3]Yongjune Kim
, Jaehong Kim, Jun Jin Kong, B. V. K. Vijaya Kumar
, Xin Li:
Verify level control criteria for multi-level cell flash memories and their applications. EURASIP J. Adv. Signal Process. 2012: 196 (2012) - [c3]Beomkyu Shin, Changkyu Seol, Jung-Soo Chung, Jun Jin Kong:
Error control coding and signal processing for flash memories. ISCAS 2012: 409-412
2000 – 2009
- 2004
- [j2]Jun Jin Kong, Keshab K. Parhi
:
Low-latency architectures for high-throughput rate Viterbi decoders. IEEE Trans. Very Large Scale Integr. Syst. 12(6): 642-651 (2004) - 2003
- [j1]Jun Jin Kong, Keshab K. Parhi
:
Interleaved Convolutional Code and Its Viterbi Decoder Architecture. EURASIP J. Adv. Signal Process. 2003(13): 1328-1334 (2003) - 2002
- [c2]Gunok Jung, Jun Jin Kong, Gerald E. Sobelman, Keshab K. Parhi
:
High-speed add-compare-select units using locally self-resetting CMOS. ISCAS (1) 2002: 889-892 - 2000
- [c1]Dai Won Kim, Taek Won Kwon, Jun Rim Choi, Jun Jin Kong:
A modified two-step SOVA-based turbo decoder with a fixed scaling factor. ISCAS 2000: 37-40
Coauthor Index
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last updated on 2024-05-08 20:57 CEST by the dblp team
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