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ORCIDItsujiro Arita
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2000 – 2009
- 2008
[j5]Toshihiro Uchibayashi, Bernady O. Apduhan, Itsujiro Arita:
Navilite: a Lightweight Indoor Location-Aware Mobile Navigation Service for the Handicapped and the Elderly. J. Mobile Multimedia 4(2): 104-117 (2008)- 2007
- [c18]Toshihiro Uchibayashi, Bernady O. Apduhan, Itsujiro Arita:
An Indoor Location-Aware Mobile Navigation Service for the Handicapped and the Elderly. MoMM 2007: 207-216 - 2003
- [j4]Toshinori Sato
, Itsujiro Arita:
Combining variable latency pipeline with instruction reuse for execution latency reduction. Syst. Comput. Jpn. 34(12): 11-21 (2003) - [j3]Takenori Koushiro, Toshinori Sato, Itsujiro Arita:
A trace-level value predictor for Contrail processors. SIGARCH Comput. Archit. News 31(3): 42-47 (2003) - 2002
- [j2]Koichiro Tanaka, Itsujiro Arita:
The development and evaluation of SHOKE2000: The PCI-based FPGA card. Syst. Comput. Jpn. 33(9): 50-57 (2002) - [c17]Toshinori Sato, Itsujiro Arita:
Simplifying Instruction Issue Logic in Superscalar Processors. DSD 2002: 341-346 - [c16]Toshinori Sato, Itsujiro Arita:
Low-Cost Value Predictors Using Frequent Value Locality. ISHPC 2002: 106-119 - [c15]Toshinori Sato, Itsujiro Arita:
Reducing Energy Consumption via Low-Cost Value Prediction. PATMOS 2002: 380-389 - [c14]Toshiyuki Yamamoto, Kou Morita, Toshinori Sato, Itsujiro Arita:
The KIT COSMOS Processor: An Application of Multi-Threading for Dynamic Optimization. PDPTA 2002: 1010-1016 - 2001
- [c13]Toshinori Sato, Itsujiro Arita:
Tolerating Transient Faults through an Instruction Reissue Mechanism. PDCS 2001: 240-247 - [c12]Toshinori Sato, Itsujiro Arita:
Execution Latency Reduction via Variable Latency Pipeline and Instruction Reuse. Euro-Par 2001: 428-438 - [c11]Toshinori Sato, Akihiko Hamano, Kiichi Sugitani, Itsujiro Arita:
Influence of Compiler Optimizations on Value Prediction. HPCN Europe 2001: 312-321 - [c10]Yasushi Shimono, Bernady O. Apduhan, Itsujiro Arita, Yoshimasa Ohnishi:
Evaluating the Performance of a DSM Cluster with Improved Communication Subsystem. ICOIN 2001: 561-567 - [c9]Toshinori Sato, Itsujiro Arita:
In Search of Efficient Reliable Processor Design. ICPP 2001: 525-532 - [c8]Toshinori Sato, Itsujiro Arita:
Evaluating Low-Cost Fault-Tolerance Mechanism for Microprocessors on Multimedia Applications. PRDC 2001: 225-232 - 2000
- [c7]Takayuki Hirahara, Takashi Yamanoue, Hiroyuki Anzai, Itsujiro Arita:
Sending an Image to a Large Number of Nodes in Short Time using TCP. IEEE International Conference on Multimedia and Expo (II) 2000: 987-990 - [c6]Toshinori Sato, Itsujiro Arita:
Partial Resolution in Data Value Predictors. ICPP 2000: 69-76 - [c5]Toshinori Sato, Itsujiro Arita:
Table size reduction for data value predictors by exploiting narrow width values. ICS 2000: 196-205 - [c4]Toshinori Sato, Itsujiro Arita:
Comprehensive Evaluation of an Instruction Reissue Mechanism. ISPAN 2000: 78-87 - [c3]Toshinori Sato, Itsujiro Arita:
The KIT COSMOS Processor: Introducing CONDOR. PDPTA 2000
1990 – 1999
- 1999
- [c2]Tatsuya Asazu, Bernady O. Apduhan, Itsujiro Arita:
Towards a Portable Cluster Computing Environment Supporting Single System Image. ICPP Workshops 1999: 488-495
1980 – 1989
- 1986
- [j1]Toshinori Sueyoshi, Keizo Saisho, Itsujiro Arita:
Performance evaluation of the binary tree access mechanism in mimd type parallel computers. Syst. Comput. Jpn. 17(9): 47-57 (1986) - 1980
- [c1]Itsujiro Arita:
Intelligent console - A universal user interface of a computer system. Operating Systems Engineering 1980: 233-250
Coauthor Index
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